著者名,論文名,雑誌名,ISSN,出版者名,出版日付,巻,号,ページ,URL,URL(DOI)
,A Test Generation Method for Path Delay Faults in Sequential Circuits with Discontinuous Reconvergence Structure,"Trans, of IEICE (DI) (in Japanese) Vol.J86-D-I, No.12",,,2003,,,872-883,https://cir.nii.ac.jp/crid/1010282256779021456,