{"@context":{"@vocab":"https://cir.nii.ac.jp/schema/1.0/","rdfs":"http://www.w3.org/2000/01/rdf-schema#","dc":"http://purl.org/dc/elements/1.1/","dcterms":"http://purl.org/dc/terms/","foaf":"http://xmlns.com/foaf/0.1/","prism":"http://prismstandard.org/namespaces/basic/2.0/","cinii":"http://ci.nii.ac.jp/ns/1.0/","datacite":"https://schema.datacite.org/meta/kernel-4/","ndl":"http://ndl.go.jp/dcndl/terms/","jpcoar":"https://github.com/JPCOAR/schema/blob/master/2.0/"},"@id":"https://cir.nii.ac.jp/crid/1050299461908606976.json","@type":"Article","productIdentifier":[{"identifier":{"@type":"URI","@value":"https://opac-t.time.u-tokai.ac.jp/iwjs0018opc/TC20003007"}}],"resourceType":"紀要論文(departmental bulletin paper)","dc:title":[{"@value":"NI, NANDおよびCYCゲートを用いた3値順序回路の一構成"}],"dcterms:alternative":[{"@value":"A Design of Ternary Sequential Logic Circuits wit NI, NAND and CYC Gates"}],"dc:language":"ja","creator":[{"@id":"https://cir.nii.ac.jp/crid/1420564276186944000","@type":"Researcher","personIdentifier":[{"@type":"KAKEN_RESEARCHERS","@value":"60229044"},{"@type":"NRID","@value":"1000060229044"},{"@type":"NRID","@value":"9000002375915"},{"@type":"NRID","@value":"9000002253112"},{"@type":"NRID","@value":"9000415143121"},{"@type":"NRID","@value":"9000397688006"},{"@type":"NRID","@value":"9000386384397"},{"@type":"NRID","@value":"9000398825678"},{"@type":"NRID","@value":"9000403159510"},{"@type":"NRID","@value":"9000415180820"},{"@type":"NRID","@value":"9000415225295"},{"@type":"NRID","@value":"9000411224792"},{"@type":"NRID","@value":"9000406046511"},{"@type":"NRID","@value":"9000415187676"},{"@type":"NRID","@value":"9000415167625"},{"@type":"NRID","@value":"9000414804002"},{"@type":"NRID","@value":"9000415147553"},{"@type":"NRID","@value":"9000001935947"},{"@type":"NRID","@value":"9000378653368"},{"@type":"NRID","@value":"9000405620681"},{"@type":"NRID","@value":"9000390914549"},{"@type":"RESEARCHMAP","@value":"https://researchmap.jp/fujimoto_kuniaki"}],"foaf:name":[{"@value":"藤本, 邦昭"}]},{"@id":"https://cir.nii.ac.jp/crid/1070299461908606978","@type":"Researcher","foaf:name":[{"@value":"佐藤, 邦夫"}]},{"@id":"https://cir.nii.ac.jp/crid/1070299461908606977","@type":"Researcher","foaf:name":[{"@value":"小高, 明夫"}]}],"publication":{"publicationIdentifier":[{"@type":"ISSN","@value":"24343633"}],"prism:publicationName":[{"@value":"東海大学紀要. 工学部"}],"dc:publisher":[{"@value":"東海大学工学部"}],"prism:publicationDate":"1988-10-30","prism:volume":"28","prism:number":"1","prism:startingPage":"63","prism:endingPage":"76"},"url":[{"@id":"https://opac-t.time.u-tokai.ac.jp/iwjs0018opc/TC20003007"}],"foaf:topic":[{"@id":"https://cir.nii.ac.jp/all?q=ternary%20sequential%20circuit","dc:title":"ternary sequential circuit"},{"@id":"https://cir.nii.ac.jp/all?q=SD-FF","dc:title":"SD-FF"},{"@id":"https://cir.nii.ac.jp/all?q=SMS-FF","dc:title":"SMS-FF"},{"@id":"https://cir.nii.ac.jp/all?q=UDT-FF","dc:title":"UDT-FF"},{"@id":"https://cir.nii.ac.jp/all?q=T-FF","dc:title":"T-FF"}],"dcterms:subject":[{"subjectScheme":"Other","notation":[{"@value":"ternary sequential circuit"}]},{"subjectScheme":"Other","notation":[{"@value":"SD-FF"}]},{"subjectScheme":"Other","notation":[{"@value":"SMS-FF"}]},{"subjectScheme":"Other","notation":[{"@value":"UDT-FF"}]},{"subjectScheme":"Other","notation":[{"@value":"T-FF"}]}],"dataSourceIdentifier":[{"@type":"IRDB","@value":"oai:irdb.nii.ac.jp:00910:0006050274"}]}