著者名,書名,版表示,出版者名,出版年,シリーズ名,番号,ISBN,ISSN,URL
"Radecka, Katarzyna and Zilic, Zeljko",Verification by error modeling : using testing techniques in hardware verification,,Kluwer Academic,2003,Frontiers in electronic testing,,1402076525,,https://cir.nii.ac.jp/crid/1130000796498681856