50-GFLOPS Floating-Point Adder and Multiplier Using Gate-Level-Pipelined Single-Flux-Quantum Logic With Frequency-Increased Clock Distribution
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- Ikki Nagaoka
- Nagoya University, Nagoya, Japan
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- Ryota Kashima
- Nagoya University, Nagoya, Japan
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- Masamitsu Tanaka
- Nagoya University, Nagoya, Japan
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- Satoshi Kawakami
- Kyushu University, Fukuoka, Japan
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- Teruo Tanimoto
- Kyushu University, Fukuoka, Japan
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- Taro Yamashita
- Nagoya University, Nagoya, Japan
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- Koji Inoue
- Kyushu University, Fukuoka, Japan
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- Akira Fujimaki
- Nagoya University, Nagoya, Japan
この論文をさがす
収録刊行物
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- IEEE Transactions on Applied Superconductivity
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IEEE Transactions on Applied Superconductivity 33 (4), 1-11, 2023-06
Institute of Electrical and Electronics Engineers (IEEE)
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詳細情報 詳細情報について
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- CRID
- 1360021390747776768
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- ISSN
- 15582515
- 23787074
- 10518223
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- 資料種別
- journal article
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- データソース種別
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- Crossref
- KAKEN
- OpenAIRE