{"@context":{"@vocab":"https://cir.nii.ac.jp/schema/1.0/","rdfs":"http://www.w3.org/2000/01/rdf-schema#","dc":"http://purl.org/dc/elements/1.1/","dcterms":"http://purl.org/dc/terms/","foaf":"http://xmlns.com/foaf/0.1/","prism":"http://prismstandard.org/namespaces/basic/2.0/","cinii":"http://ci.nii.ac.jp/ns/1.0/","datacite":"https://schema.datacite.org/meta/kernel-4/","ndl":"http://ndl.go.jp/dcndl/terms/","jpcoar":"https://github.com/JPCOAR/schema/blob/master/2.0/"},"@id":"https://cir.nii.ac.jp/crid/1360021395986710784.json","@type":"Article","productIdentifier":[{"identifier":{"@type":"DOI","@value":"10.1145/3007787.3001165"}},{"identifier":{"@type":"URI","@value":"https://dl.acm.org/doi/10.1145/3007787.3001165"}},{"identifier":{"@type":"URI","@value":"https://dl.acm.org/doi/pdf/10.1145/3007787.3001165"}}],"dc:title":[{"@value":"Minerva"}],"dcterms:alternative":[{"@value":"enabling low-power, highly-accurate deep neural network accelerators"}],"description":[{"type":"abstract","notation":[{"@value":"<jats:p>The continued success of Deep Neural Networks (DNNs) in classification tasks has sparked a trend of accelerating their execution with specialized hardware. While published designs easily give an order of magnitude improvement over general-purpose hardware, few look beyond an initial implementation. This paper presents Minerva, a highly automated co-design approach across the algorithm, architecture, and circuit levels to optimize DNN hardware accelerators. Compared to an established fixed-point accelerator baseline, we show that fine-grained, heterogeneous datatype optimization reduces power by 1.5×; aggressive, inline predication and pruning of small activity values further reduces power by 2.0×; and active hardware fault detection coupled with domain-aware error mitigation eliminates an additional 2.7× through lowering SRAM voltages. Across five datasets, these optimizations provide a collective average of 8.1× power reduction over an accelerator baseline without compromising DNN model accuracy. Minerva enables highly accurate, ultra-low power DNN accelerators (in the range of tens of milliwatts), making it feasible to deploy DNNs in power-constrained IoT and mobile devices.</jats:p>"}]}],"creator":[{"@id":"https://cir.nii.ac.jp/crid/1380021395986710784","@type":"Researcher","foaf:name":[{"@value":"Brandon Reagen"}],"jpcoar:affiliationName":[{"@value":"Harvard University"}]},{"@id":"https://cir.nii.ac.jp/crid/1380021395986710790","@type":"Researcher","foaf:name":[{"@value":"Paul Whatmough"}],"jpcoar:affiliationName":[{"@value":"Harvard University"}]},{"@id":"https://cir.nii.ac.jp/crid/1380021395986710792","@type":"Researcher","foaf:name":[{"@value":"Robert Adolf"}],"jpcoar:affiliationName":[{"@value":"Harvard University"}]},{"@id":"https://cir.nii.ac.jp/crid/1380021395986710788","@type":"Researcher","foaf:name":[{"@value":"Saketh Rama"}],"jpcoar:affiliationName":[{"@value":"Harvard University"}]},{"@id":"https://cir.nii.ac.jp/crid/1380021395986710786","@type":"Researcher","foaf:name":[{"@value":"Hyunkwang Lee"}],"jpcoar:affiliationName":[{"@value":"Harvard University"}]},{"@id":"https://cir.nii.ac.jp/crid/1380021395986710785","@type":"Researcher","foaf:name":[{"@value":"Sae Kyu Lee"}],"jpcoar:affiliationName":[{"@value":"Harvard University"}]},{"@id":"https://cir.nii.ac.jp/crid/1380021395986710787","@type":"Researcher","foaf:name":[{"@value":"José Miguel Hernández-Lobato"}],"jpcoar:affiliationName":[{"@value":"Harvard University"}]},{"@id":"https://cir.nii.ac.jp/crid/1380021395986710789","@type":"Researcher","foaf:name":[{"@value":"Gu-Yeon Wei"}],"jpcoar:affiliationName":[{"@value":"Harvard University"}]},{"@id":"https://cir.nii.ac.jp/crid/1380021395986710791","@type":"Researcher","foaf:name":[{"@value":"David Brooks"}],"jpcoar:affiliationName":[{"@value":"Harvard University"}]}],"publication":{"publicationIdentifier":[{"@type":"PISSN","@value":"01635964"}],"prism:publicationName":[{"@value":"ACM SIGARCH Computer Architecture News"}],"dc:publisher":[{"@value":"Association for Computing Machinery (ACM)"}],"prism:publicationDate":"2016-06-18","prism:volume":"44","prism:number":"3","prism:startingPage":"267","prism:endingPage":"278"},"reviewed":"false","dc:rights":["https://www.acm.org/publications/policies/copyright_policy#Background"],"url":[{"@id":"https://dl.acm.org/doi/10.1145/3007787.3001165"},{"@id":"https://dl.acm.org/doi/pdf/10.1145/3007787.3001165"}],"createdAt":"2016-10-13","modifiedAt":"2025-06-18","relatedProduct":[{"@id":"https://cir.nii.ac.jp/crid/1361975846137515392","@type":"Article","resourceType":"学術雑誌論文(journal article)","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"A stochastic-computing based deep learning framework using adiabatic quantum-flux-parametron superconducting technology"}]}],"dataSourceIdentifier":[{"@type":"CROSSREF","@value":"10.1145/3007787.3001165"},{"@type":"CROSSREF","@value":"10.1145/3307650.3322270_references_DOI_GaiYJyl8NOvfgo8RnfzBhppM3am"}]}