SOI wafer fabricated with extremely thick deposited BOX layer using a surface activated bonding technique at room temperature
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説明
<jats:title>Abstract</jats:title> <jats:p>The fabrication cost of bonded silicon on insulator (SOI) wafers for customized power devices is high owing to the high temperature required and the very long fabrication process involving both thermal oxidation and bonding. In addition, SOI wafers are contaminated with metallic impurities during the formation of the buried oxide (BOX) layer and the bonding of a silicon layer on the BOX layer. Therefore, we propose an alternative SOI wafer fabrication method combining BOX layer deposition and surface activated bonding at room temperature in a vacuum without any voids. There is also no fixed charge in the deposited BOX layer, and the breakdown voltage of this layer is 11–12 MV cm<jats:sup>−1</jats:sup>, the same as that for a thermal oxide layer.</jats:p>
収録刊行物
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- Japanese Journal of Applied Physics
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Japanese Journal of Applied Physics 59 (SB), SBBB02-, 2019-11-26
IOP Publishing
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詳細情報 詳細情報について
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- CRID
- 1360284924859687040
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- NII論文ID
- 210000157437
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- ISSN
- 13474065
- 00214922
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- データソース種別
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