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- Yosuke Ueno
- RIKEN, Wako, Saitama, Japan
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- Yuna Tomida
- University of Tokyo, Tokyo, Japan
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- Teruo Tanimoto
- Kyushu University, Fukuoka, Japan
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- Masamitsu Tanaka
- Nagoya University, Nagoya, Aichi, Japan
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- Yutaka Tabuchi
- RIKEN, Wako, Saitama, Japan
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- Koji Inoue
- Kyushu University, Fukuoka, Japan
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- Hiroshi Nakamura
- University of Tokyo, Tokyo, Japan
書誌事項
- 公開日
- 2024-01
- 資源種別
- journal article
- 権利情報
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- https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html
- https://doi.org/10.15223/policy-029
- https://doi.org/10.15223/policy-037
- DOI
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- 10.1109/lca.2023.3322700
- 10.48550/arxiv.2310.01630
- 公開者
- Institute of Electrical and Electronics Engineers (IEEE)
この論文をさがす
説明
The bandwidth limit between cryogenic and room-temperature environments is a critical bottleneck in superconducting noisy intermediate-scale quantum computers. This paper presents the first trial of algorithm-aware system-level optimization to solve this issue by targeting the quantum approximate optimization algorithm. Our counter-based cryogenic architecture using single-flux quantum logic shows exponential bandwidth reduction and decreases heat inflow and peripheral power consumption of inter-temperature cables, which contributes to the scalability of superconducting quantum computers.
4 pages, 5 figures, 1 table. Accepted by IEEE Computer Architecture Letters,
収録刊行物
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- IEEE Computer Architecture Letters
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IEEE Computer Architecture Letters 23 (1), 9-12, 2024-01
Institute of Electrical and Electronics Engineers (IEEE)
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キーワード
詳細情報 詳細情報について
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- CRID
- 1360584340713460352
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- ISSN
- 15566064
- 24732575
- 15566056
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- 資料種別
- journal article
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- データソース種別
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- Crossref
- KAKEN
- OpenAIRE