LSI‐oriented scanning systems using tree structures

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<jats:title>Abstract</jats:title><jats:p>Two types of scanning systems using <jats:italic>N</jats:italic>‐ary tree structures are proposed for high‐speed intelligent processing in an SIMD parallel processor. The scanning systems are constructed by connecting operating elements to each other with hierarchical bypasses or hierarchical and selective propagation paths. After evaluating their operating times, the amount of hardware, and LSI implementation, the following conclusions were reached: (1) the number of serially operating elements in the propagation path is only <jats:italic>O</jats:italic>(<jats:italic>N</jats:italic> log<jats:sub><jats:italic>N</jats:italic></jats:sub> <jats:italic>M</jats:italic>); (2) enlarging the <jats:italic>N</jats:italic>‐value decreases the amount of hardware; (3) the selective‐type scanning system is twice as fast as the bypass‐type system although both require almost the same amount of hardware; and (4) a 4<jats:sup>2</jats:sup>‐ary tree structure leads to a simple and dense chip layout.</jats:p>

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