著者名,論文名,雑誌名,ISSN,出版者名,出版日付,巻,号,ページ,URL,URL(DOI)
Hanli Liu and Atsushi Shirane and Kenichi Okada and Zheng Sun and Hongye Huang and Wei Deng and Teerachot Siriburanon and Jian Pang and Yun Wang and Rui Wu and Teruki Someya,A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS,IEEE Journal of Solid-State Circuits,0018-9200,Institute of Electrical and Electronics Engineers (IEEE),2019-12,54,12,3478-3492,https://cir.nii.ac.jp/crid/1361418519949195008,https://doi.org/10.1109/jssc.2019.2936967