{"@context":{"@vocab":"https://cir.nii.ac.jp/schema/1.0/","rdfs":"http://www.w3.org/2000/01/rdf-schema#","dc":"http://purl.org/dc/elements/1.1/","dcterms":"http://purl.org/dc/terms/","foaf":"http://xmlns.com/foaf/0.1/","prism":"http://prismstandard.org/namespaces/basic/2.0/","cinii":"http://ci.nii.ac.jp/ns/1.0/","datacite":"https://schema.datacite.org/meta/kernel-4/","ndl":"http://ndl.go.jp/dcndl/terms/","jpcoar":"https://github.com/JPCOAR/schema/blob/master/2.0/"},"@id":"https://cir.nii.ac.jp/crid/1361699994777554944.json","@type":"Article","productIdentifier":[{"identifier":{"@type":"DOI","@value":"10.9790/2834-09353643"}}],"dc:title":[{"@value":"Design and Implementation of 4-Bit Arithmetic and Logic Unit Chip with the Constraint of Power Consumption"}],"creator":[{"@id":"https://cir.nii.ac.jp/crid/1381699994777554946","@type":"Researcher","foaf:name":[{"@value":"Priyanka Yadav"}]},{"@id":"https://cir.nii.ac.jp/crid/1381699994777554944","@type":"Researcher","foaf:name":[{"@value":"Gaurav Kumar"}]},{"@id":"https://cir.nii.ac.jp/crid/1381699994777554945","@type":"Researcher","foaf:name":[{"@value":"Sumita Gupta"}]}],"publication":{"publicationIdentifier":[{"@type":"PISSN","@value":"22788735"},{"@type":"EISSN","@value":"22782834"}],"prism:publicationName":[{"@value":"IOSR Journal of Electronics and Communication Engineering"}],"dc:publisher":[{"@value":"IOSR Journals"}],"prism:publicationDate":"2014","prism:volume":"9","prism:number":"3","prism:startingPage":"36","prism:endingPage":"43"},"reviewed":"false","createdAt":"2014-06-25","modifiedAt":"2014-06-25","relatedProduct":[{"@id":"https://cir.nii.ac.jp/crid/1360285710315557120","@type":"Article","resourceType":"学術雑誌論文(journal article)","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing"}]},{"@id":"https://cir.nii.ac.jp/crid/1360572092699106560","@type":"Article","resourceType":"学術雑誌論文(journal article)","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon"}]},{"@id":"https://cir.nii.ac.jp/crid/1360853567675816192","@type":"Article","resourceType":"学術雑誌論文(journal article)","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"An Elastic Neural Network Toward Multi-Grained Re-configurable Accelerator"}]},{"@id":"https://cir.nii.ac.jp/crid/1390001288150966144","@type":"Article","resourceType":"学術雑誌論文(journal article)","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation"}]}],"dataSourceIdentifier":[{"@type":"CROSSREF","@value":"10.9790/2834-09353643"},{"@type":"CROSSREF","@value":"10.1109/newcas49341.2020.9159845_references_DOI_XMSZUd2SlNY2LlHCx3i4XPPmE3l"},{"@type":"CROSSREF","@value":"10.1109/socc46988.2019.1570548015_references_DOI_XMSZUd2SlNY2LlHCx3i4XPPmE3l"},{"@type":"CROSSREF","@value":"10.1109/mm.2018.2873953_references_DOI_XMSZUd2SlNY2LlHCx3i4XPPmE3l"},{"@type":"CROSSREF","@value":"10.1587/transfun.e102.a.878_references_DOI_XMSZUd2SlNY2LlHCx3i4XPPmE3l"}]}