{"@context":{"@vocab":"https://cir.nii.ac.jp/schema/1.0/","rdfs":"http://www.w3.org/2000/01/rdf-schema#","dc":"http://purl.org/dc/elements/1.1/","dcterms":"http://purl.org/dc/terms/","foaf":"http://xmlns.com/foaf/0.1/","prism":"http://prismstandard.org/namespaces/basic/2.0/","cinii":"http://ci.nii.ac.jp/ns/1.0/","datacite":"https://schema.datacite.org/meta/kernel-4/","ndl":"http://ndl.go.jp/dcndl/terms/","jpcoar":"https://github.com/JPCOAR/schema/blob/master/2.0/"},"@id":"https://cir.nii.ac.jp/crid/1361699995790515328.json","@type":"Article","productIdentifier":[{"identifier":{"@type":"DOI","@value":"10.1109/55.877205"}},{"identifier":{"@type":"URI","@value":"http://xplorestaging.ieee.org/ielx5/55/18989/00877205.pdf?arnumber=877205"}},{"identifier":{"@type":"NAID","@value":"80011940657"}}],"dc:title":[{"@value":"NROM: A novel localized trapping, 2-bit nonvolatile memory cell"}],"creator":[{"@id":"https://cir.nii.ac.jp/crid/1583668926508624768","@type":"Researcher","foaf:name":[{"@value":"B. Eitan"}]},{"@id":"https://cir.nii.ac.jp/crid/1381699995790515329","@type":"Researcher","foaf:name":[{"@value":"P. Pavan"}]},{"@id":"https://cir.nii.ac.jp/crid/1381699995790515328","@type":"Researcher","foaf:name":[{"@value":"I. Bloom"}]},{"@id":"https://cir.nii.ac.jp/crid/1381699995790515331","@type":"Researcher","foaf:name":[{"@value":"E. Aloni"}]},{"@id":"https://cir.nii.ac.jp/crid/1381699995790515330","@type":"Researcher","foaf:name":[{"@value":"A. Frommer"}]},{"@id":"https://cir.nii.ac.jp/crid/1381699995790515333","@type":"Researcher","foaf:name":[{"@value":"D. Finzi"}]}],"publication":{"publicationIdentifier":[{"@type":"PISSN","@value":"07413106"},{"@type":"EISSN","@value":"15580563"}],"prism:publicationName":[{"@value":"IEEE Electron Device Letters"}],"dc:publisher":[{"@value":"Institute of Electrical and Electronics Engineers (IEEE)"}],"prism:publicationDate":"2000-11","prism:volume":"21","prism:number":"11","prism:startingPage":"543","prism:endingPage":"545"},"reviewed":"false","dc:rights":["https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html"],"url":[{"@id":"http://xplorestaging.ieee.org/ielx5/55/18989/00877205.pdf?arnumber=877205"}],"createdAt":"2002-08-24","modifiedAt":"2021-11-29","relatedProduct":[{"@id":"https://cir.nii.ac.jp/crid/1360003446853625216","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Band-to-Band Hot-hole Erase Characteristics of 2-Bit/cell NOR-type Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory Cell with Spacer-type Storage Node on Recessed Channel Structure"}]},{"@id":"https://cir.nii.ac.jp/crid/1360003446855331200","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Source Side Injection Programmed P-Channel Self-Aligned-Nitride One-Time Programming Cell for 90 nm Logic Nonvolatile Memory Applications"}]},{"@id":"https://cir.nii.ac.jp/crid/1360003446855784832","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"A Direct Observation of the Distributions of Local Trapped-Charges and the Interface-States near the Drain Region of the Silicon–Oxide–Nitride–Oxide–Silicon Device for Reliable Four-Bit/Cell Operations"}]},{"@id":"https://cir.nii.ac.jp/crid/1360003446856871936","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-Side Assisted Erase Scheme Using Minimum Channel Length/Width Standard Complemental Metal–Oxide–Semiconductor Single Transistor Cell"}]},{"@id":"https://cir.nii.ac.jp/crid/1360003449885185792","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Investigations of an Independent Double-Gated Polycrystalline Silicon Nanowire Thin Film Transistor for Nonvolatile Memory Operations"}]},{"@id":"https://cir.nii.ac.jp/crid/1360003449886567168","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Study Trapped Charge Distribution in P-Channel Silicon–Oxide–Nitride–Oxide–Silicon Memory Device Using Dynamic Programming Scheme"}]},{"@id":"https://cir.nii.ac.jp/crid/1360003449891526656","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Fabrication of solid-state secondary battery using semiconductors and evaluation of its charge/discharge characteristics"}]},{"@id":"https://cir.nii.ac.jp/crid/1360003449891960320","@type":"Article","resourceType":"学術雑誌論文(journal article)","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"In situ formation of Hf-based metal/oxide/nitride/oxide/silicon structure for nonvolatile memory application"}]},{"@id":"https://cir.nii.ac.jp/crid/1360284921812196096","@type":"Article","resourceType":"学術雑誌論文(journal article)","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Visualization of Electrons Localized in Metal–Oxide–Nitride–Oxide–Semiconductor Flash Memory Thin Gate Films by Detecting High-Order Nonlinear Permittivity Using Scanning Nonlinear Dielectric Microscopy"}]},{"@id":"https://cir.nii.ac.jp/crid/1360284921829514624","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Retention Mechanism of Localized Silicon–Oxide–Nitride–Oxide–Silicon Embedded NOR Device"}]},{"@id":"https://cir.nii.ac.jp/crid/1360284921831094656","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Novel Self-Aligned Nitride One Time Programming with 2-bit/Cell Based on Pure 90-nm Complementary Metal–Oxide–Semiconductor Logic Technology"}]},{"@id":"https://cir.nii.ac.jp/crid/1360284921831484160","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Mobile-Ion-Induced Charge Loss Failure in Silicon–Oxide–Nitride–Oxide–Silicon Two-Bit Storage Flash Memory"}]},{"@id":"https://cir.nii.ac.jp/crid/1360284921832044032","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Charge Localization during Program and Retention in Nitrided Read Only Memory-Like Nonvolatile Memory Devices"}]},{"@id":"https://cir.nii.ac.jp/crid/1360285708882435584","@type":"Article","resourceType":"学術雑誌論文(journal article)","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Scanning nonlinear dielectric microscopy observation of accumulated charges in metal-SiO2-SiN-SiO2-Si flash memory by detecting higher-order nonlinear permittivity"}]},{"@id":"https://cir.nii.ac.jp/crid/1360566396806196224","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Nano-Scale Memory Characteristics of Silicon Nitride Charge Trapping Layer with Silicon Nanocrystals"}]},{"@id":"https://cir.nii.ac.jp/crid/1360566396806737152","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Retention Reliability Improvement of Silicon–Oxide–Nitride–Oxide–Silicon Nonvolatile Memory with N<sub>2</sub>O Oxidation Tunnel Oxide"}]},{"@id":"https://cir.nii.ac.jp/crid/1360566396806824576","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Design of Unique Four-Bit/Cell Polycrystalline Silicon–Oxide–Silicon Nitride–Oxide–Silicon Devices Utilizing Vertical Channel of Silicon Pillar"}]},{"@id":"https://cir.nii.ac.jp/crid/1360566396810051968","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Substrate-Bias Assisted Hot Electron Injection Method for High-Speed, Low-Voltage, and Multi-Bit Flash Memories"}]},{"@id":"https://cir.nii.ac.jp/crid/1360566399839045888","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-Side Assisted Erase Scheme Using Minimum Channel Length/Width Standard Complemental Metal–Oxide–Semiconductor Single Transistor Cell"}]},{"@id":"https://cir.nii.ac.jp/crid/1360566399839689984","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"A 2-bit/Cell Gate-All-Around Flash Memory of Self-Assembled Silicon Nanocrystals"}]},{"@id":"https://cir.nii.ac.jp/crid/1360566399843154560","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Low-frequency noise in 2-bit poly-Si TANOS flash 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silicon–oxide–nitride–oxide–silicon NAND flash memory for high-density nonvolatile memory"}]},{"@id":"https://cir.nii.ac.jp/crid/1390001204375736832","@type":"Article","relationType":["isCitedBy"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme"}]},{"@id":"https://cir.nii.ac.jp/crid/1390001206264317184","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Highly Manufacturable and Reliable 80-nm Gate Twin Silicon-Oxide-Nitride-Oxide-Silicon Memory Transistor"}]},{"@id":"https://cir.nii.ac.jp/crid/1390282679352448896","@type":"Article","relationType":["isCitedBy"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure"}]},{"@id":"https://cir.nii.ac.jp/crid/1390282679356241792","@type":"Article","resourceType":"学術雑誌論文(journal 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Structure"}]},{"@id":"https://cir.nii.ac.jp/crid/1572261552489719296","@type":"Article","relationType":["isCitedBy"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Novel Structures for a 2-Bit per Cell of Nonvolatile Memory Using an Asymmetric Double Gate"}]},{"@id":"https://cir.nii.ac.jp/crid/1572824500485488640","@type":"Article","relationType":["isCitedBy"],"jpcoar:relatedTitle":[{"@language":"en","@value":"NeoFlash^【○!R】-True Logic Based 0.18μm Single Poly Embedded SONOS Flash"}]},{"@id":"https://cir.nii.ac.jp/crid/1573387452279444224","@type":"Article","relationType":["isCitedBy"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Review of Device Technologies of Flash Memories"}]}],"dataSourceIdentifier":[{"@type":"CROSSREF","@value":"10.1109/55.877205"},{"@type":"CIA","@value":"80011940657"},{"@type":"CROSSREF","@value":"10.7567/jjap.52.04cd01_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.46.6463_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.46.l798_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.50.085002_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.51.04dd02_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.7567/jjap.50.085002_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.7567/jjap.50.124201_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.7567/jjap.57.041201_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.7567/jjap.57.114201_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.45.l998_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.49.100001_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/apex.5.036602_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1063/1.4769352_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.46.7237_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.50.124201_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.7567/jjap.53.094001_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.44.2710_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.44.l1214_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1109/jssc.2011.2147030_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.7567/jjap.52.021302_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.46.6589_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.48.066510_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.49.04dd12_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.49.084301_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.49.114203_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.7567/jjap.54.064201_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.7567/jjap.57.04fe07_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.44.4825_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.44.6380_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.35848/1347-4065/ac340c_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.47.2687_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.49.04dd05_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.7567/apex.8.094201_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.7567/jjap.51.04dd02_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.7567/jjap.54.014101_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1587/transele.e95.c.564_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.44.6441_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.47.8369_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.45.l807_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"},{"@type":"CROSSREF","@value":"10.1143/jjap.45.l1027_references_DOI_5SisqkQU7MDmBYrlXegWTncvRHo"}]}