{"@context":{"@vocab":"https://cir.nii.ac.jp/schema/1.0/","rdfs":"http://www.w3.org/2000/01/rdf-schema#","dc":"http://purl.org/dc/elements/1.1/","dcterms":"http://purl.org/dc/terms/","foaf":"http://xmlns.com/foaf/0.1/","prism":"http://prismstandard.org/namespaces/basic/2.0/","cinii":"http://ci.nii.ac.jp/ns/1.0/","datacite":"https://schema.datacite.org/meta/kernel-4/","ndl":"http://ndl.go.jp/dcndl/terms/","jpcoar":"https://github.com/JPCOAR/schema/blob/master/2.0/"},"@id":"https://cir.nii.ac.jp/crid/1363670318263684992.json","@type":"Article","productIdentifier":[{"identifier":{"@type":"DOI","@value":"10.1109/iedm.2007.4418963"}},{"identifier":{"@type":"URI","@value":"http://xplorestaging.ieee.org/ielx5/4418847/4418848/04418963.pdf?arnumber=4418963"}}],"dc:title":[{"@value":"Integrated MEMS LC Resonator with Sealed Air-Suspended Structure for Single-Chip RF LSIs"}],"description":[{"notation":[{"@value":"This paper describes an integrated MEMS LC resonator that consists of a MEMS inductor and varactor. The resonator features a sealed air-suspended structure: the inductor and varactor are suspended above a CMOS LSI to improve their performance, and they are sealed with a film to protect them during packaging. The quality factor of the inductor is four times higher than that of a CMOS top-layer-metal inductor, and the varactor has a tuning ratio of 100% at about 5-V applied voltage. The resonator is applied to a voltage- controlled oscillator to show its effectiveness for the development of single-chip RF LSIs."}]}],"creator":[{"@id":"https://cir.nii.ac.jp/crid/1383670318263684994","@type":"Researcher","foaf:name":[{"@value":"K. Kuwabara"}]},{"@id":"https://cir.nii.ac.jp/crid/1383670318263685122","@type":"Researcher","foaf:name":[{"@value":"N. Sato"}]},{"@id":"https://cir.nii.ac.jp/crid/1383670318263684993","@type":"Researcher","foaf:name":[{"@value":"H. Morimura"}]},{"@id":"https://cir.nii.ac.jp/crid/1383670318263684996","@type":"Researcher","foaf:name":[{"@value":"J. Kodate"}]},{"@id":"https://cir.nii.ac.jp/crid/1383670318263684998","@type":"Researcher","foaf:name":[{"@value":"M. Nakamura"}]},{"@id":"https://cir.nii.ac.jp/crid/1383670318263685121","@type":"Researcher","foaf:name":[{"@value":"M. Ugajin"}]},{"@id":"https://cir.nii.ac.jp/crid/1383670318263684995","@type":"Researcher","foaf:name":[{"@value":"T. Kamei"}]},{"@id":"https://cir.nii.ac.jp/crid/1383670318263685120","@type":"Researcher","foaf:name":[{"@value":"K. Kudou"}]},{"@id":"https://cir.nii.ac.jp/crid/1383670318263684997","@type":"Researcher","foaf:name":[{"@value":"K. Machida"}]},{"@id":"https://cir.nii.ac.jp/crid/1383670318263684992","@type":"Researcher","foaf:name":[{"@value":"H. Ishii"}]}],"publication":{"prism:publicationName":[{"@value":"2007 IEEE International Electron Devices Meeting"}],"dc:publisher":[{"@value":"IEEE"}],"prism:publicationDate":"2007","prism:startingPage":"423","prism:endingPage":"426"},"reviewed":"false","url":[{"@id":"http://xplorestaging.ieee.org/ielx5/4418847/4418848/04418963.pdf?arnumber=4418963"}],"createdAt":"2008-01-04","modifiedAt":"2017-03-16","relatedProduct":[{"@id":"https://cir.nii.ac.jp/crid/1360283693065412352","@type":"Article","resourceType":"学術雑誌論文(journal article)","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@value":"Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems"}]},{"@id":"https://cir.nii.ac.jp/crid/1390282680189522176","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Physical design challenges to nano-CMOS circuits"}]}],"dataSourceIdentifier":[{"@type":"CROSSREF","@value":"10.1109/iedm.2007.4418963"},{"@type":"OPENAIRE","@value":"doi_dedup___::60c1d28fc2380a3ba88865e3ea46f827"},{"@type":"CROSSREF","@value":"10.1587/elex.6.703_references_DOI_7PYkL715a1VAq9hwKxXuG9boj91"},{"@type":"CROSSREF","@value":"10.1109/ted.2010.2099870_references_DOI_7PYkL715a1VAq9hwKxXuG9boj91"}]}