{"@context":{"@vocab":"https://cir.nii.ac.jp/schema/1.0/","rdfs":"http://www.w3.org/2000/01/rdf-schema#","dc":"http://purl.org/dc/elements/1.1/","dcterms":"http://purl.org/dc/terms/","foaf":"http://xmlns.com/foaf/0.1/","prism":"http://prismstandard.org/namespaces/basic/2.0/","cinii":"http://ci.nii.ac.jp/ns/1.0/","datacite":"https://schema.datacite.org/meta/kernel-4/","ndl":"http://ndl.go.jp/dcndl/terms/","jpcoar":"https://github.com/JPCOAR/schema/blob/master/2.0/"},"@id":"https://cir.nii.ac.jp/crid/1390001205212416640.json","@type":"Article","productIdentifier":[{"identifier":{"@type":"DOI","@value":"10.1587/elex.7.1796"}},{"identifier":{"@type":"URI","@value":"http://www.jstage.jst.go.jp/article/elex/7/24/7_24_1796/_pdf"}},{"identifier":{"@type":"NAID","@value":"130000401455"}}],"dc:title":[{"@language":"en","@value":"Cell placement of MCM for reliability optimization"}],"dc:language":"en","description":[{"type":"abstract","notation":[{"@language":"en","@value":"Since modern MCM (Multi Chip Module) is required to provide higher performance, MCM's density and power consumption has been increased very rapidly. Increase of chip density and power consumption lead to hot spots which accelerate the device's life time and result in device failure in the long run. In this paper, a new placement method is presented to improve the MCM's reliability using a TPSA (Two-Phase Simulated Annealing) algorithm. The TPSA searches the lowest failure rate placement of MCM perturbing higher failure rate phase and lower failure rate phase at the same time to generate a new movement. The proposed algorithm is applied to the IBM (International Business Machines) MCM device for searching an optimal solution and for comparing optimized results with other optimization results. The result shows improvement in reliability and temperature distribution satisfying constraints."}],"abstractLicenseFlag":"disallow"}],"creator":[{"@id":"https://cir.nii.ac.jp/crid/1410001205212416640","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000021112447"}],"foaf:name":[{"@language":"en","@value":"Kim Joonyun"}],"jpcoar:affiliationName":[{"@language":"en","@value":"Electronics Department, Korea Aerospace Research Institute"}]}],"publication":{"publicationIdentifier":[{"@type":"EISSN","@value":"13492543"},{"@type":"LISSN","@value":"13492543"}],"prism:publicationName":[{"@language":"en","@value":"IEICE Electronics Express"},{"@language":"en","@value":"IEICE Electron. Express"}],"dc:publisher":[{"@language":"en","@value":"The Institute of Electronics, Information and Communication Engineers"},{"@language":"ja","@value":"一般社団法人 電子情報通信学会"}],"prism:publicationDate":"2010","prism:volume":"7","prism:number":"24","prism:startingPage":"1796","prism:endingPage":"1801"},"reviewed":"false","url":[{"@id":"http://www.jstage.jst.go.jp/article/elex/7/24/7_24_1796/_pdf"}],"availableAt":"2010","foaf:topic":[{"@id":"https://cir.nii.ac.jp/all?q=reliability%20optimization","dc:title":"reliability optimization"},{"@id":"https://cir.nii.ac.jp/all?q=two-phase%20simulated%20annealing","dc:title":"two-phase simulated annealing"},{"@id":"https://cir.nii.ac.jp/all?q=cell%20placement","dc:title":"cell placement"}],"relatedProduct":[{"@id":"https://cir.nii.ac.jp/crid/1360022497271626496","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Macrocell placement with temperature profile optimization"}]},{"@id":"https://cir.nii.ac.jp/crid/1361137044209794176","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Dual-tapered-piston (DTP) module cooling for IBM Enterprise System/9000 systems"}]},{"@id":"https://cir.nii.ac.jp/crid/1362262945850461568","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Temperature acceleration models in reliability predictions: Justification & improvements"}]},{"@id":"https://cir.nii.ac.jp/crid/1362825893466389504","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Placement for reliability and routability of convectively cooled PWBs"}]},{"@id":"https://cir.nii.ac.jp/crid/1362825894262696576","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Optimization by Simulated Annealing"}]},{"@id":"https://cir.nii.ac.jp/crid/1364233269379825408","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"A reliability-driven placement procedure based on thermal-force model"}]},{"@id":"https://cir.nii.ac.jp/crid/1364233269680506112","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Thermal placement algorithm based on heat conduction analogy"}]},{"@id":"https://cir.nii.ac.jp/crid/1390565134827043200","@type":"Article","resourceType":"学術雑誌論文(journal article)","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Thermal placement on PCB of components including 3D ICs"}]}],"dataSourceIdentifier":[{"@type":"JALC","@value":"oai:japanlinkcenter.org:0036118394"},{"@type":"CROSSREF","@value":"10.1587/elex.7.1796"},{"@type":"CIA","@value":"130000401455"},{"@type":"CROSSREF","@value":"10.1587/elex.17.20190737_references_DOI_6TAXzk7TyIdGkacA3S6tTvBkOFz"}]}