{"@context":{"@vocab":"https://cir.nii.ac.jp/schema/1.0/","rdfs":"http://www.w3.org/2000/01/rdf-schema#","dc":"http://purl.org/dc/elements/1.1/","dcterms":"http://purl.org/dc/terms/","foaf":"http://xmlns.com/foaf/0.1/","prism":"http://prismstandard.org/namespaces/basic/2.0/","cinii":"http://ci.nii.ac.jp/ns/1.0/","datacite":"https://schema.datacite.org/meta/kernel-4/","ndl":"http://ndl.go.jp/dcndl/terms/","jpcoar":"https://github.com/JPCOAR/schema/blob/master/2.0/"},"@id":"https://cir.nii.ac.jp/crid/1390001206309716096.json","@type":"Article","productIdentifier":[{"identifier":{"@type":"DOI","@value":"10.1587/transfun.e93.a.1594"}},{"identifier":{"@type":"URI","@value":"http://www.jstage.jst.go.jp/article/transfun/E93.A/9/E93.A_9_1594/_pdf"}},{"identifier":{"@type":"NAID","@value":"10027637809"}}],"dc:title":[{"@language":"en","@value":"A High-Throughput Binary Arithmetic Coding Architecture for H.264/AVC CABAC"}],"dc:language":"en","description":[{"type":"abstract","notation":[{"@language":"en","@value":"In this paper, we propose a high-throughput binary arithmetic coding architecture for CABAC (Context Adaptive Binary Arithmetic Coding) which is one of the entropy coding tools used in the H.264/AVC main and high profiles. The full CABAC encoding functions, including binarization, context model selection, arithmetic encoding and bits generation, are implemented in this proposal. The binarization and context model selection are implemented in a proposed binarizer, in which a FIFO is used to pack the binarization results and output 4 <i>bins</i> in one clock. The arithmetic encoding and bits generation are implemented in a four-stage pipeline with the encoding ability of 4 <i>bins</i>/clock. In order to improve the processing speed, the context variables access and update for 4 <i>bins</i> are paralleled and the pipeline path is balanced. Also, because of the outstanding bits issue, a bits packing and generation strategy for 4 <i>bins</i> paralleled processing is proposed. After implemented in verilog-HDL and synthesized with Synopsys Design Compiler using 90nm libraries, this proposal can work at the clock frequency of 250MHz and takes up about 58K standard cells, 3.2Kbits register files and 27.6K bits ROM. The throughput of processing 1000M <i>bins</i> per second can be achieved in this proposal for the HDTV applications."}],"abstractLicenseFlag":"disallow"}],"creator":[{"@id":"https://cir.nii.ac.jp/crid/1410001206309716097","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000018527667"}],"foaf:name":[{"@language":"en","@value":"LIU Yizhong"}],"jpcoar:affiliationName":[{"@language":"en","@value":"Computer Systems Engineering, Institute of Technology and Science, Graduate School of Engineering, Tokushima University"}]},{"@id":"https://cir.nii.ac.jp/crid/1420282801205006848","@type":"Researcher","personIdentifier":[{"@type":"KAKEN_RESEARCHERS","@value":"10380130"},{"@type":"NRID","@value":"1000010380130"},{"@type":"NRID","@value":"9000006359164"},{"@type":"NRID","@value":"9000311503552"},{"@type":"NRID","@value":"9000402384797"},{"@type":"NRID","@value":"9000018852671"},{"@type":"NRID","@value":"9000365044504"},{"@type":"NRID","@value":"9000279644445"},{"@type":"NRID","@value":"9000004352967"},{"@type":"NRID","@value":"9000283354494"},{"@type":"NRID","@value":"9000412274830"},{"@type":"NRID","@value":"9000411103231"},{"@type":"NRID","@value":"9000375905468"},{"@type":"NRID","@value":"9000300212058"},{"@type":"NRID","@value":"9000018527668"},{"@type":"NRID","@value":"9000412274827"},{"@type":"NRID","@value":"9000021272496"},{"@type":"NRID","@value":"9000309571024"},{"@type":"NRID","@value":"9000413566310"},{"@type":"NRID","@value":"9000021308418"},{"@type":"NRID","@value":"9000345287801"},{"@type":"NRID","@value":"9000021343293"},{"@type":"NRID","@value":"9000257861488"},{"@type":"NRID","@value":"9000402437513"},{"@type":"NRID","@value":"9000292181907"},{"@type":"RESEARCHMAP","@value":"https://researchmap.jp/read0119895"}],"foaf:name":[{"@language":"en","@value":"SONG Tian"}],"jpcoar:affiliationName":[{"@language":"en","@value":"Computer Systems Engineering, Institute of Technology and Science, Graduate School of Engineering, Tokushima University"}]},{"@id":"https://cir.nii.ac.jp/crid/1030003658364232960","@type":"Researcher","personIdentifier":[{"@type":"KAKEN_RESEARCHERS","@value":"20170962"},{"@type":"NRID","@value":"1000020170962"},{"@type":"NRID","@value":"9000006359165"},{"@type":"NRID","@value":"9000311503554"},{"@type":"NRID","@value":"9000402384798"},{"@type":"NRID","@value":"9000018852672"},{"@type":"NRID","@value":"9000365044507"},{"@type":"NRID","@value":"9000003949903"},{"@type":"NRID","@value":"9000283354495"},{"@type":"NRID","@value":"9000004775555"},{"@type":"NRID","@value":"9000415191238"},{"@type":"NRID","@value":"9000375905472"},{"@type":"NRID","@value":"9000415148867"},{"@type":"NRID","@value":"9000018527669"},{"@type":"NRID","@value":"9000319064683"},{"@type":"NRID","@value":"9000415221960"},{"@type":"NRID","@value":"9000004848418"},{"@type":"NRID","@value":"9000309571025"},{"@type":"NRID","@value":"9000021308438"},{"@type":"NRID","@value":"9000345287804"},{"@type":"NRID","@value":"9000256072462"},{"@type":"NRID","@value":"9000021343300"},{"@type":"NRID","@value":"9000398274365"},{"@type":"NRID","@value":"9000257861491"},{"@type":"NRID","@value":"9000402437514"},{"@type":"NRID","@value":"9000292181909"},{"@type":"NRID","@value":"9000017475107"},{"@type":"RESEARCHMAP","@value":"https://researchmap.jp/simamoto"}],"foaf:name":[{"@language":"en","@value":"SHIMAMOTO Takashi"}],"jpcoar:affiliationName":[{"@language":"en","@value":"Computer Systems Engineering, Institute of Technology and Science, Graduate School of Engineering, Tokushima University"}]}],"publication":{"publicationIdentifier":[{"@type":"PISSN","@value":"09168508"},{"@type":"EISSN","@value":"17451337"},{"@type":"NCID","@value":"AA10826239"}],"prism:publicationName":[{"@language":"en","@value":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"},{"@language":"en","@value":"IEICE Trans. Fundamentals"}],"dc:publisher":[{"@language":"en","@value":"The Institute of Electronics, Information and Communication Engineers"},{"@language":"ja","@value":"一般社団法人 電子情報通信学会"}],"prism:publicationDate":"2010","prism:volume":"E93-A","prism:number":"9","prism:startingPage":"1594","prism:endingPage":"1604"},"reviewed":"false","url":[{"@id":"http://www.jstage.jst.go.jp/article/transfun/E93.A/9/E93.A_9_1594/_pdf"}],"availableAt":"2010","foaf:topic":[{"@id":"https://cir.nii.ac.jp/all?q=H.264/AVC%20encoder","dc:title":"H.264/AVC encoder"},{"@id":"https://cir.nii.ac.jp/all?q=CABAC","dc:title":"CABAC"},{"@id":"https://cir.nii.ac.jp/all?q=entropy%20coding","dc:title":"entropy coding"},{"@id":"https://cir.nii.ac.jp/all?q=binary%20arithmetic%20coding","dc:title":"binary arithmetic coding"},{"@id":"https://cir.nii.ac.jp/all?q=VLSI","dc:title":"VLSI"}],"relatedProduct":[{"@id":"https://cir.nii.ac.jp/crid/1360011144251947392","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"A Hardwired Context-Based Adaptive Binary Arithmetic Encoder for H. 264 Advanced Video Coding"}]},{"@id":"https://cir.nii.ac.jp/crid/1360574094320281344","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"A High-Performance Architecture of the Double-Mode Binary Coder for H.264.AVC"}]},{"@id":"https://cir.nii.ac.jp/crid/1361137044916142464","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard"}]},{"@id":"https://cir.nii.ac.jp/crid/1361699994943896448","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file"}]},{"@id":"https://cir.nii.ac.jp/crid/1361981469351868928","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Efficient pipelined CABAC encoding architecture"}]},{"@id":"https://cir.nii.ac.jp/crid/1362262945964322944","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file"}]},{"@id":"https://cir.nii.ac.jp/crid/1363670319593284352","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Full RDO-Support Power-Aware CABAC Encoder With Efficient Context Access"}]},{"@id":"https://cir.nii.ac.jp/crid/1363670319921962752","@type":"Article","relationType":["references","cites"],"jpcoar:relatedTitle":[{"@value":"Overview of the H.264/AVC video coding standard"}]},{"@id":"https://cir.nii.ac.jp/crid/1570291226279789440","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@language":"en","@value":"A high performance CABAC encoder"}]},{"@id":"https://cir.nii.ac.jp/crid/1570854176477612416","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Efficient pipelined CABAC encoding architecture"}]},{"@id":"https://cir.nii.ac.jp/crid/1571135651455856384","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@language":"en","@value":"A high-performance architecture of the double-mode binary coder for H.262.AVC"}]},{"@id":"https://cir.nii.ac.jp/crid/1571135651738039424","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Context-based binary arithmetic coding in the H.264/AVC video compression standard"}]},{"@id":"https://cir.nii.ac.jp/crid/1571698601422180352","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@language":"en","@value":"High-throughput architecture for H.264/AVC CABAC compression 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coding"}]},{"@id":"https://cir.nii.ac.jp/crid/1573950400977023232","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@language":"en","@value":"A novel architecture for high performance CABAC encoder"}]},{"@id":"https://cir.nii.ac.jp/crid/1573950400977027968","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@language":"en","@value":"A VLSI architecture for high performance CABAC encoding"}]},{"@id":"https://cir.nii.ac.jp/crid/1574231875953732352","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@language":"en","@value":"A high throughput binary arithmetic coding engine for H.264/AVC"}]},{"@id":"https://cir.nii.ac.jp/crid/1574231876469177984","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@language":"en","@value":"A 130-nm 6-GHz 256×32 bit leakage-tolerant register file"}]}],"dataSourceIdentifier":[{"@type":"JALC","@value":"oai:japanlinkcenter.org:0035541879"},{"@type":"CROSSREF","@value":"10.1587/transfun.e93.a.1594"},{"@type":"CIA","@value":"10027637809"},{"@type":"OPENAIRE","@value":"doi_dedup___::88868fdb66b8f3c73224627eb779ba99"}]}