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The SIMD cores support 8/16bits SIMD MAC instructions, and vertical vector access. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. This hierarchical network can provide more than 192GB/s low latency inter-core BW in average. The 4-ports L2 cache architecture is also designed to provide 192GB/s L2 cache BW. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Compared with MOESI, 67.8% of L1 cache energy can be saved in 32 cores case. The whole system including 32 vector cores, 256KB L2 cache, 64-bit DDRII PHY and two PLL units, occupy 25mm<sup>2</sup> in 65nm CMOS. It can achieve a peak performance of 375 GMACs and 98 GMACs/W at 1.2V."}],"abstractLicenseFlag":"disallow"}],"creator":[{"@id":"https://cir.nii.ac.jp/crid/1410001206311013504","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000018279919"}],"foaf:name":[{"@language":"en","@value":"HE Xun"}],"jpcoar:affiliationName":[{"@language":"en","@value":"Graduate School of Information, Production and Systems, Waseda University"}]},{"@id":"https://cir.nii.ac.jp/crid/1410001206311478147","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000006914338"}],"foaf:name":[{"@language":"en","@value":"JIN Xin"}],"jpcoar:affiliationName":[{"@language":"en","@value":"Information Technology Research Organization, Waseda University"}]},{"@id":"https://cir.nii.ac.jp/crid/1410001206311478145","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000017675402"}],"foaf:name":[{"@language":"en","@value":"WANG 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