{"@context":{"@vocab":"https://cir.nii.ac.jp/schema/1.0/","rdfs":"http://www.w3.org/2000/01/rdf-schema#","dc":"http://purl.org/dc/elements/1.1/","dcterms":"http://purl.org/dc/terms/","foaf":"http://xmlns.com/foaf/0.1/","prism":"http://prismstandard.org/namespaces/basic/2.0/","cinii":"http://ci.nii.ac.jp/ns/1.0/","datacite":"https://schema.datacite.org/meta/kernel-4/","ndl":"http://ndl.go.jp/dcndl/terms/","jpcoar":"https://github.com/JPCOAR/schema/blob/master/2.0/"},"@id":"https://cir.nii.ac.jp/crid/1390282680189102464.json","@type":"Article","productIdentifier":[{"identifier":{"@type":"DOI","@value":"10.1587/elex.11.20141071"}},{"identifier":{"@type":"URI","@value":"https://www.jstage.jst.go.jp/article/elex/11/24/11_11.20141071/_pdf"}},{"identifier":{"@type":"NAID","@value":"130004713146"}}],"dc:title":[{"@language":"en","@value":"Optimization of periphery circuits in a 1K-bit PCRAM chip for highly reliable write and read operations"}],"dc:language":"en","description":[{"type":"abstract","notation":[{"@language":"en","@value":"A 1K-bit phase change random access memory (PCRAM) with improved periphery circuits for better reliable operations has been successfully developed in 130 nm CMOS technology. A flexible write driver is proposed to provide a novel continuous step-down pulses by studying programming strategies while a reliable read circuit is designed by investigating the special transition characteristics of PCRAM, leading to an effective write operation and a non-destructive read operation without any additional changes of the storage states. In addition, a large sense margin has been achieved and the read results corresponding well with the write operations, which demonstrate the influences of technology variations have been considerably decreased with the proposed periphery circuits."}],"abstractLicenseFlag":"disallow"}],"creator":[{"@id":"https://cir.nii.ac.jp/crid/1410282680189102464","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000273021012"}],"foaf:name":[{"@language":"en","@value":"Wang Qian"}],"jpcoar:affiliationName":[{"@language":"en","@value":"State Key Laboratory of Functional Materials for Informatics, Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}]},{"@id":"https://cir.nii.ac.jp/crid/1410282680189102468","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000273021011"}],"foaf:name":[{"@language":"en","@value":"Chen Houpeng"}],"jpcoar:affiliationName":[{"@language":"en","@value":"State Key Laboratory of Functional Materials for Informatics, Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}]},{"@id":"https://cir.nii.ac.jp/crid/1410282680189102465","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000273021013"}],"foaf:name":[{"@language":"en","@value":"Li Xi"}],"jpcoar:affiliationName":[{"@language":"en","@value":"State Key Laboratory of Functional Materials for Informatics, Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}]},{"@id":"https://cir.nii.ac.jp/crid/1410282680189102336","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000273021014"}],"foaf:name":[{"@language":"en","@value":"Zhang Yiyun"}],"jpcoar:affiliationName":[{"@language":"en","@value":"State Key Laboratory of Functional Materials for Informatics, Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}]},{"@id":"https://cir.nii.ac.jp/crid/1410282680189102337","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000273021010"}],"foaf:name":[{"@language":"en","@value":"Fan Xi"}],"jpcoar:affiliationName":[{"@language":"en","@value":"State Key Laboratory of Functional Materials for Informatics, Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}]},{"@id":"https://cir.nii.ac.jp/crid/1410282680189102338","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000273021018"}],"foaf:name":[{"@language":"en","@value":"Song Zhitang"}],"jpcoar:affiliationName":[{"@language":"en","@value":"State Key Laboratory of Functional Materials for Informatics, Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}]},{"@id":"https://cir.nii.ac.jp/crid/1410282680189102466","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000273021017"}],"foaf:name":[{"@language":"en","@value":"Chen Yifeng"}],"jpcoar:affiliationName":[{"@language":"en","@value":"State Key Laboratory of Functional Materials for Informatics, Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}]},{"@id":"https://cir.nii.ac.jp/crid/1410282680189102339","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000273021016"}],"foaf:name":[{"@language":"en","@value":"Jin Rong"}],"jpcoar:affiliationName":[{"@language":"en","@value":"State Key Laboratory of Functional Materials for Informatics, Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}]},{"@id":"https://cir.nii.ac.jp/crid/1410282680189102467","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000273021015"}],"foaf:name":[{"@language":"en","@value":"Hu Jiajun"}],"jpcoar:affiliationName":[{"@language":"en","@value":"State Key Laboratory of Functional Materials for Informatics, Shanghai Key Laboratory of Nanofabrication Technology for Memory, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences"}]}],"publication":{"publicationIdentifier":[{"@type":"EISSN","@value":"13492543"},{"@type":"LISSN","@value":"13492543"}],"prism:publicationName":[{"@language":"en","@value":"IEICE Electronics Express"},{"@language":"en","@value":"IEICE Electron. Express"}],"dc:publisher":[{"@language":"en","@value":"The Institute of Electronics, Information and Communication Engineers"},{"@language":"ja","@value":"一般社団法人 電子情報通信学会"}],"prism:publicationDate":"2014","prism:volume":"11","prism:number":"24","prism:startingPage":"20141071","prism:endingPage":"20141071"},"reviewed":"false","url":[{"@id":"https://www.jstage.jst.go.jp/article/elex/11/24/11_11.20141071/_pdf"}],"availableAt":"2014","foaf:topic":[{"@id":"https://cir.nii.ac.jp/all?q=PCRAM","dc:title":"PCRAM"},{"@id":"https://cir.nii.ac.jp/all?q=periphery%20circuits","dc:title":"periphery circuits"},{"@id":"https://cir.nii.ac.jp/all?q=reliability","dc:title":"reliability"},{"@id":"https://cir.nii.ac.jp/all?q=resistance%20distribution","dc:title":"resistance distribution"},{"@id":"https://cir.nii.ac.jp/all?q=step-down%20pulse","dc:title":"step-down pulse"}],"relatedProduct":[{"@id":"https://cir.nii.ac.jp/crid/1360292619239006848","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"CMOS current mode flash analog to digital converter"}]},{"@id":"https://cir.nii.ac.jp/crid/1360566399839568640","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Optimization of Anomalous Cells with High SET Resistance in Phase Change Memory Arrays"}]},{"@id":"https://cir.nii.ac.jp/crid/1360574094356464640","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Circuit implementation to describe the physical behavior of phase change memory"}]},{"@id":"https://cir.nii.ac.jp/crid/1360847871786263808","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Microstructural Characterization in Reliability Measurement of Phase Change Random Access Memory"}]},{"@id":"https://cir.nii.ac.jp/crid/1360855568959669760","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Evolution of cell resistance, threshold voltage and crystallization temperature during cycling of line-cell phase-change random access memory"}]},{"@id":"https://cir.nii.ac.jp/crid/1361418518606708992","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Program circuit for a phase change memory array with 2 MB/s write throughput for embedded applications"}]},{"@id":"https://cir.nii.ac.jp/crid/1361418519570146304","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Highly reliable 50nm contact cell technology for 256Mb PRAM"}]},{"@id":"https://cir.nii.ac.jp/crid/1361699993578099328","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"The future of phase-change semiconductor memory devices"}]},{"@id":"https://cir.nii.ac.jp/crid/1362262943648885760","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"RESET Distribution Improvement of Phase Change Memory: The Impact of Pre-Programming"}]},{"@id":"https://cir.nii.ac.jp/crid/1362544420603208704","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Analysis of the effect of boron doping on GeTe Phase Change Memories"}]},{"@id":"https://cir.nii.ac.jp/crid/1362825893854002176","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth"}]},{"@id":"https://cir.nii.ac.jp/crid/1362825896287722240","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"The race of phase change memories to nanoscale storage and applications"}]},{"@id":"https://cir.nii.ac.jp/crid/1363388844666320000","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Enhanced write performance of a 64Mb phase-change random access memory"}]},{"@id":"https://cir.nii.ac.jp/crid/1363388845085457664","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Observation and modeling of polycrystalline grain formation in Ge2Sb2Te5"}]},{"@id":"https://cir.nii.ac.jp/crid/1363670319442875648","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Non-volatile memory technologies for beyond 2010"}]},{"@id":"https://cir.nii.ac.jp/crid/1363670319871579648","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Reliability characterization of Phase Change Memory"}]},{"@id":"https://cir.nii.ac.jp/crid/1363670320177597824","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Reversible Electrical Switching Phenomena in Disordered Structures"}]},{"@id":"https://cir.nii.ac.jp/crid/1364233269324729216","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Recovery and Drift Dynamics of Resistance and Threshold Voltages in Phase-Change Memories"}]},{"@id":"https://cir.nii.ac.jp/crid/1390001205212329728","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Methods to speed up read operation in a 64 Mbit phase change memory chip"}]},{"@id":"https://cir.nii.ac.jp/crid/1390001205219493504","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Enhanced read performance for phase change memory using a reference column"}]},{"@id":"https://cir.nii.ac.jp/crid/1390564238098470656","@type":"Article","relationType":["isReferencedBy"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Near-threshold SIDO DC-DC converter with a high-precision ZCD for phase change memory chip"}]}],"dataSourceIdentifier":[{"@type":"JALC","@value":"oai:japanlinkcenter.org:2000004237"},{"@type":"CROSSREF","@value":"10.1587/elex.11.20141071"},{"@type":"CIA","@value":"130004713146"},{"@type":"CROSSREF","@value":"10.1587/elex.16.20190250_references_DOI_NrPE6UVYvYfPnK9v7wKCL0tTGtt"},{"@type":"CROSSREF","@value":"10.1587/elex.12.20150792_references_DOI_NrPE6UVYvYfPnK9v7wKCL0tTGtt"},{"@type":"CROSSREF","@value":"10.1587/elex.14.20170032_references_DOI_NrPE6UVYvYfPnK9v7wKCL0tTGtt"}]}