{"@context":{"@vocab":"https://cir.nii.ac.jp/schema/1.0/","rdfs":"http://www.w3.org/2000/01/rdf-schema#","dc":"http://purl.org/dc/elements/1.1/","dcterms":"http://purl.org/dc/terms/","foaf":"http://xmlns.com/foaf/0.1/","prism":"http://prismstandard.org/namespaces/basic/2.0/","cinii":"http://ci.nii.ac.jp/ns/1.0/","datacite":"https://schema.datacite.org/meta/kernel-4/","ndl":"http://ndl.go.jp/dcndl/terms/","jpcoar":"https://github.com/JPCOAR/schema/blob/master/2.0/"},"@id":"https://cir.nii.ac.jp/crid/1390282680190260352.json","@type":"Article","productIdentifier":[{"identifier":{"@type":"DOI","@value":"10.1587/elex.13.20160061"}},{"identifier":{"@type":"URI","@value":"https://www.jstage.jst.go.jp/article/elex/13/6/13_13.20160061/_pdf"}},{"identifier":{"@type":"NAID","@value":"130005139712"}}],"dc:title":[{"@language":"en","@value":"A 128 Kb HfO<sub>2</sub> ReRAM with Novel Double-Reference and Dynamic-Tracking scheme for write yield improvement"}],"dc:language":"en","description":[{"type":"abstract","notation":[{"@language":"en","@value":"A 128 Kb HfO<sub>2</sub> Resistive Random Access Memory (ReRAM) chip is developed based on HHNEC 0.13 µm 1P8M CMOS process. ReRAM is suffering the write yield problem due to the tail-bit issues and large resistance variations at high temperature. In this paper a novel Double-Reference and Dynamic-Tracking Write (DR-DTW) scheme and a Dynamic read scheme are proposed to fix these issues. The experiment results show that the tail-bit issues are almost eliminated and the write yield is improved greatly compared with traditional write scheme."}],"abstractLicenseFlag":"disallow"}],"creator":[{"@id":"https://cir.nii.ac.jp/crid/1410282680190260352","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000318139013"}],"foaf:name":[{"@language":"en","@value":"Chen Chengying"}],"jpcoar:affiliationName":[{"@language":"en","@value":"Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences"}]},{"@id":"https://cir.nii.ac.jp/crid/1410282680190260354","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000318139014"}],"foaf:name":[{"@language":"en","@value":"Sun Hongbin"}],"jpcoar:affiliationName":[{"@language":"en","@value":"School of Electrical and Information Engineering, Xi’an Jiaotong University"}]},{"@id":"https://cir.nii.ac.jp/crid/1410282680190260353","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000318139015"}],"foaf:name":[{"@language":"en","@value":"Shen Haihua"}],"jpcoar:affiliationName":[{"@language":"en","@value":"School of Computer and Control Engineering, University of Chinese Academy of Sciences"}]},{"@id":"https://cir.nii.ac.jp/crid/1410282680190260355","@type":"Researcher","personIdentifier":[{"@type":"NRID","@value":"9000318139016"}],"foaf:name":[{"@language":"en","@value":"Zhang Feng"}],"jpcoar:affiliationName":[{"@language":"en","@value":"Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences"}]}],"publication":{"publicationIdentifier":[{"@type":"EISSN","@value":"13492543"},{"@type":"LISSN","@value":"13492543"}],"prism:publicationName":[{"@language":"en","@value":"IEICE Electronics Express"},{"@language":"en","@value":"IEICE Electron. Express"}],"dc:publisher":[{"@language":"en","@value":"The Institute of Electronics, Information and Communication Engineers"},{"@language":"ja","@value":"一般社団法人 電子情報通信学会"}],"prism:publicationDate":"2016","prism:volume":"13","prism:number":"6","prism:startingPage":"20160061","prism:endingPage":"20160061"},"reviewed":"false","url":[{"@id":"https://www.jstage.jst.go.jp/article/elex/13/6/13_13.20160061/_pdf"}],"availableAt":"2016","foaf:topic":[{"@id":"https://cir.nii.ac.jp/all?q=ReRAM","dc:title":"ReRAM"},{"@id":"https://cir.nii.ac.jp/all?q=Double-Reference","dc:title":"Double-Reference"},{"@id":"https://cir.nii.ac.jp/all?q=Dynamic-Tracking","dc:title":"Dynamic-Tracking"},{"@id":"https://cir.nii.ac.jp/all?q=Dynamic%20read","dc:title":"Dynamic read"}],"relatedProduct":[{"@id":"https://cir.nii.ac.jp/crid/1360292619652518912","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Optimal migration route of Cu in HfO<sub>2</sub>"}]},{"@id":"https://cir.nii.ac.jp/crid/1360574095234728192","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"A novel high reliability CMOS SRAM cell"}]},{"@id":"https://cir.nii.ac.jp/crid/1360855568555690880","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Simulation study of conductive filament growth dynamics in oxide-electrolyte-based ReRAM"}]},{"@id":"https://cir.nii.ac.jp/crid/1360855568945727872","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM"}]},{"@id":"https://cir.nii.ac.jp/crid/1361981470206798720","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Effects of interaction between defects on the uniformity of doping HfO<sub>2</sub>-based RRAM: a first principle study"}]},{"@id":"https://cir.nii.ac.jp/crid/1361981471383395968","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput"}]},{"@id":"https://cir.nii.ac.jp/crid/1362262944266592640","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process"}]},{"@id":"https://cir.nii.ac.jp/crid/1362544418696172288","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Non-volatile resistive switching for advanced memory applications"}]},{"@id":"https://cir.nii.ac.jp/crid/1362544419370092672","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Metal dopants in HfO<sub>2</sub>-based RRAM: first principle study"}]},{"@id":"https://cir.nii.ac.jp/crid/1362544421121799680","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3 V"}]},{"@id":"https://cir.nii.ac.jp/crid/1362825893331691520","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Highly scalable non-volatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses"}]},{"@id":"https://cir.nii.ac.jp/crid/1363107369530613248","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Characteristics of HfO<sub>2</sub>/Hf-based bipolar resistive memories"}]},{"@id":"https://cir.nii.ac.jp/crid/1363107369702577408","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"High-speed low-power voltage-programmed driving scheme for AMOLED displays"}]},{"@id":"https://cir.nii.ac.jp/crid/1363388844027778176","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"Conductive Filament Scaling of ${\\rm TaO}_{\\rm x}$ Bipolar ReRAM for Improving Data Retention Under Low Operation Current"}]},{"@id":"https://cir.nii.ac.jp/crid/1363951795921137920","@type":"Article","relationType":["references"],"jpcoar:relatedTitle":[{"@value":"A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability"}]}],"dataSourceIdentifier":[{"@type":"JALC","@value":"oai:japanlinkcenter.org:2000929603"},{"@type":"CROSSREF","@value":"10.1587/elex.13.20160061"},{"@type":"CIA","@value":"130005139712"}]}