LEO Single Event Upset Emulator for Validation of FPGA Based Avionics Systems

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Abstract

This paper presents a complete design and implementation of a Single Event Upset (SEU) emulation system that can be used to inject faults Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA). The FPGA is used to implement an avionics system for a small satellite. The fault injector emulates the expected Single Event Upset (SEU) rate as it would be in the Low Earth Orbit (LEO) of the polar orbiting satellites at inclinations close to 98° deg., and altitude of about 670 km. The emulator injects faults in the configuration bit-stream of the FPGA without stopping its operation. It makes use of the partial reconfiguration feature of today's FPGAs. This provides a facility to assess the design performance in space even if radiation testing will not be conducted before launching. Also, it simulates the expected upset rate and hence calculates the corresponding data failure rates for Triple Modular Redundancy (TMR) fault tolerant designs. The system was implemented using the Xilinx Virtex- LX50T FPGA. The FPGA suffered system failures during the fault injection test. It recovered about 50% of the failures. TMR simulation at an upset rate of 0.1 upsets (per bit per second) for a data size of 2048 bits showed that about 33% of the faults will be fully corrected.

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