A High-Signal-Integrity PCB Trace with Embedded Chip Capacitors and Its Design Methodology Using a Genetic Algorithm
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- Yasunaga Moritoshi
- Graduate School of Systems and Information Engineering, University of Tsukuba
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- Matsuoka Shumpei
- Graduate School of Systems and Information Engineering, University of Tsukuba
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- Hoshino Yuya
- Graduate School of Systems and Information Engineering, University of Tsukuba
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- Matsumoto Takashi
- Graduate School of Systems and Information Engineering, University of Tsukuba
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- Odaira Tetsuya
- Graduate School of Systems and Information Engineering, University of Tsukuba
抄録
<p>Signal integrity (SI) degradation in printed circuit boards (PCBs) in the gigahertz domain has become an increasingly serious problem because of the difficulty of developing and implementing impedance matching designs. In this paper, we propose a novel trace structure called a capacitor segmental transmission line (C-STL) and a design methodology for C-STL capacitances to overcome the problem of SI degradation. In a C-STL, reflected waves are intentionally generated by mismatching the impedance of adjacent segments with embedded chip capacitors connected to the PCB trace. These reflected waves interfere with the distorted digital signal and shape it into an ideal waveform. In the proposed C-STL design methodology, a genetic algorithm is used to overcome the combinatorial explosion problem posed by the chip capacitor selection required in the design. A C-STL prototype was fabricated, and its high SI improvement capabilities were demonstrated by eye diagram measurements.</p>
収録刊行物
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- Transactions of The Japan Institute of Electronics Packaging
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Transactions of The Japan Institute of Electronics Packaging 12 (0), E19-007-1-E19-007-9, 2019
一般社団法人エレクトロニクス実装学会
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詳細情報 詳細情報について
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- CRID
- 1390283659832572160
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- NII論文ID
- 130007772175
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- ISSN
- 18848028
- 18833365
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
- KAKEN
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- 抄録ライセンスフラグ
- 使用不可