Theoretical estimation of current imbalance in multichip power module using resistance matrix
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- Nomura Katsuya
- School of Engineering, Kwansei Gakuin University
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- Sawada Takashi
- Institute of Innovation for Future Society, Nagoya University
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- Tadano Hiroshi
- Institute of Innovation for Future Society, Nagoya University
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- Takagi Kenichi
- Institute of Innovation for Future Society, Nagoya University
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- Shiozaki Koji
- Institute of Innovation for Future Society, Nagoya University
書誌事項
- 公開日
- 2025-11-25
- DOI
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- 10.1587/elex.22.20250509
- 公開者
- 一般社団法人 電子情報通信学会
この論文をさがす
説明
<p>This paper describes a theoretical method to estimate the current imbalance based on the resistance matrix in a multichip power module. It is derived that the current through each device can be calculated based on the terminal voltage, the resistance matrix of the module, and the on-resistance of each device. The resistance matrix of the module can be easily obtained using parasitic extraction simulation tools. By using circuit simulations for 4-, 6-, and 12-parallel module structures, it is confirmed that the proposed method can accurately estimate the current imbalance.</p>
収録刊行物
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- IEICE Electronics Express
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IEICE Electronics Express 22 (22), 20250509-20250509, 2025-11-25
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390306428918704128
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- ISSN
- 13492543
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
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- 抄録ライセンスフラグ
- 使用不可
