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- MOCHIZUKI Akira
- Research Institute of Electrical Communication, Tohoku University
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- HANYU Takahiro
- Research Institute of Electrical Communication, Tohoku University
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説明
A new multiple-valued current-mode (MVCM) logic circuit using substrate bias control is proposed for low-power VLSI systems at higher clock frequency. Since a multi-level threshold value is represented as a threshold voltage of an MOS transistor, a voltage comparator is realized by a single MOS transistor. As a result, two basic components, a comparator and an output generator in the MVCM logic circuit can be merged into a single MOS differential-pair circuit where the threshold voltages of MOS transistors are controlled by substrate biasing. Moreover, the leakage current is also reduced using substrate bias control. As a typical example of an arithmetic circuit, a radix-2 signed-digit full adder using the proposed circuit is implemented in a 0.18-μm CMOS technology. Its dynamic and static power dissipations are reduced to about 79 percent and 14 percent, respectively, in comparison with those of the corresponding binary CMOS implementation at the supply voltage of 1.8 V and the clock frequency of 500MHz.
収録刊行物
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- IEICE transactions on electronics
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IEICE transactions on electronics 87 (4), 582-588, 2004-04-01
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詳細情報 詳細情報について
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- CRID
- 1570291227535242112
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- NII論文ID
- 110003214894
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- NII書誌ID
- AA10826283
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- ISSN
- 09168524
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- 本文言語コード
- en
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- データソース種別
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- CiNii Articles