Author,Title,Journal,ISSN,Publisher,Date,Volume,Number,Page,URL,URL(DOI)
GENDAI Yuji,An analysis method of ADC sampling delay dependency on input signal using Verilog-A as a test bench,"電気学会研究会資料. ECT, 電子回路研究会",,,2007-06-29,2007,46,25-30,https://cir.nii.ac.jp/crid/1570572700539935104,