{"@context":{"@vocab":"https://cir.nii.ac.jp/schema/1.0/","rdfs":"http://www.w3.org/2000/01/rdf-schema#","dc":"http://purl.org/dc/elements/1.1/","dcterms":"http://purl.org/dc/terms/","foaf":"http://xmlns.com/foaf/0.1/","prism":"http://prismstandard.org/namespaces/basic/2.0/","cinii":"http://ci.nii.ac.jp/ns/1.0/","datacite":"https://schema.datacite.org/meta/kernel-4/","ndl":"http://ndl.go.jp/dcndl/terms/","jpcoar":"https://github.com/JPCOAR/schema/blob/master/2.0/"},"@id":"https://cir.nii.ac.jp/crid/1571698602017190400.json","@type":"Article","productIdentifier":[{"identifier":{"@type":"NAID","@value":"110002775377"}}],"dc:title":[{"@language":"ja","@value":"論理関数のXOR分解アルゴリズムについて"},{"@language":"en","@value":"On Exclusive-Or Decomposition Algorithms of Logic Functions"}],"dc:language":"ja","description":[{"type":"abstract","notation":[{"@language":"ja","@value":"ファクタードフォームはテクノロジ独立なレベルでの回路構造,および回路面積の見積りやテクノロジマッピングの初期解に適した論理関数表現であるが, AND/OR演算子のみを用いているのでXORを含んだ回路に対しては適切な論理式表現とならない.本稿では, XOR演算子を含んだファクタードフォームを生成するための一手法として,関数のXOR分解について取り上げ,2種類のアルゴリズムを提案する.一つは互いに素なサポートを持つ関数への分解を行なうアルゴリズムであり,もう一つはただ一つの変数を共通のサポートとして持つ関数への分解を行なうアルゴリズムである.どちらも二分決定グラフを用いて効率良く実行することができるので,従来のファクタリングアルゴリズムと組み合わせることで,より簡潔な論理式表現を得ることができる."},{"@language":"en","@value":"Factored form is a natural way to express a logic function with keeping multi-level logic circuit's structure. Thus, its literal count is generally used for evaluating circuit area in technology independent level. And factored form is also a good start point to technology mapping. However, in the case of technology mapping including XOR cells, factored form is not a good measure nor a good start point, because it consists of only AND/OR terms. So, effective algorithms to find a good logic expression including XOR terms are required. This paper describes novel XOR factoring algorithms that a find disjoint support decomposition or a single overlapping support decomposition. Implemented with Binary Decision Diagrams, these algorithms are very efficient. Combining these XOR factoring algorithms with the conventional AND/OR factoring algorithms, simpler logic expressions are expected to be derived."}]}],"creator":[{"@id":"https://cir.nii.ac.jp/crid/1581698602017190400","@type":"Researcher","foaf:name":[{"@language":"ja","@value":"松永 裕介"},{"@language":"en","@value":"MATSUNAGA Yusuke"}],"jpcoar:affiliationName":[{"@language":"ja","@value":"(株)富士通研究所"},{"@language":"en","@value":"Fujitsu Laboratories LTD."}]}],"publication":{"publicationIdentifier":[{"@type":"ISSN","@value":"09196072"},{"@type":"NCID","@value":"AN10096105"}],"prism:publicationName":[{"@value":"情報処理学会研究報告. ARC,計算機アーキテクチャ研究会報告"},{"@language":"en","@value":"IPSJ SIG Notes"}],"dc:publisher":[{"@value":"一般社団法人情報処理学会"},{"@language":"en","@value":"Information Processing Society of Japan (IPSJ)"}],"prism:publicationDate":"1996-12-12","prism:volume":"121","prism:startingPage":"1","prism:endingPage":"8"},"foaf:topic":[{"@id":"https://cir.nii.ac.jp/all?q=%E8%AB%96%E7%90%86%E5%90%88%E6%88%90","dc:title":"論理合成"},{"@id":"https://cir.nii.ac.jp/all?q=%E9%96%A2%E6%95%B0%E5%88%86%E8%A7%A3","dc:title":"関数分解"},{"@id":"https://cir.nii.ac.jp/all?q=%E4%BA%8C%E5%88%86%E6%B1%BA%E5%AE%9A%E3%82%B0%E3%83%A9%E3%83%95","dc:title":"二分決定グラフ"},{"@id":"https://cir.nii.ac.jp/all?q=logic%20synthesis","dc:title":"logic synthesis"},{"@id":"https://cir.nii.ac.jp/all?q=function%20decomposition","dc:title":"function decomposition"},{"@id":"https://cir.nii.ac.jp/all?q=binary%20decision%20diagrams","dc:title":"binary decision diagrams"}],"relatedProduct":[{"@id":"https://cir.nii.ac.jp/crid/1361137043960735360","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@value":"MIS: A Multiple-Level Logic Optimization System"}]},{"@id":"https://cir.nii.ac.jp/crid/1363951795450564992","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@value":"Graph-Based Algorithms for Boolean Function Manipulation"}]},{"@id":"https://cir.nii.ac.jp/crid/1570291225584698368","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Toward a mixed exclusive-/inclusive orfactored form"}]},{"@id":"https://cir.nii.ac.jp/crid/1570572702386253312","@type":"Article","relationType":["isCitedBy"],"jpcoar:relatedTitle":[{"@language":"en","@value":"パストランジスタ論理合成手法の検討"},{"@language":"en","@value":"A Study of Pass-Transistor Logic Synthesis"}]},{"@id":"https://cir.nii.ac.jp/crid/1570572702484479232","@type":"Article","relationType":["isCitedBy"],"jpcoar:relatedTitle":[{"@language":"ja","@value":"パストランジスタ論理合成手法の検討"},{"@language":"en","@value":"A Study of Pass-Transistor Logic Synthesis"}]},{"@id":"https://cir.nii.ac.jp/crid/1571980075444960512","@type":"Article","relationType":["cites"]},{"@id":"https://cir.nii.ac.jp/crid/1573387450328179840","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Logic synthesis with XOR gates"}]},{"@id":"https://cir.nii.ac.jp/crid/1573668926425957888","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@language":"en","@value":"DAGON : Technology Binding and Local Optimization by DAG Matching"}]},{"@id":"https://cir.nii.ac.jp/crid/1574231875258308992","@type":"Article","relationType":["cites"],"jpcoar:relatedTitle":[{"@language":"en","@value":"Multilevel Logic Synthesis Based on Functional Decision Diagrams"}]}],"dataSourceIdentifier":[{"@type":"CIA","@value":"110002775377"}]}