Noise Suppression Scheme for Giga-Scale DRAM with Hundreds of I/Os

7 References
  • TAKASHIMA D.
    ULSI Research Laboratories, Research and Development Center, TOSHIBA Corporation
  • OHWAKI Y.
    ULSI Research Laboratories, Research and Development Center, TOSHIBA Corporation
  • WATANABE S.
    ULSI Research Laboratories, Research and Development Center, TOSHIBA Corporation
  • OHUCHI K.
    ULSI Research Laboratories, Research and Development Center, TOSHIBA Corporation
  • MATSUNAGA J.
    ULSI Research Laboratories, Research and Development Center, TOSHIBA Corporation

Bibliographic Information

Other Title
  • 大容量・高バンド幅DRAMを実現する電源ノイズ低減法

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Description

The power / ground line noise due to the parasitic inductances of package and PCB causes serious problems for realizing giga-bit scale and ultra-high bandwidth DRAMs. First, this paper proposes "Constant-Current Voltage-Down Converter" which requires constant current through external Vdd/Vss pins, resulting in the minimum di/dt. Second, this paper proposes "Partially Inverted Data Bus Architecture" which reduces simultaneous switching noise to (1/n) using only (n-1) bit flag signals, and realizes wide 128 or 256 bit I/Os at 1G Hz.

Journal

  • Technical report of IEICE. SDM

    Technical report of IEICE. SDM 96 (225), 43-49, 1996-08-22

    The Institute of Electronics, Information and Communication Engineers

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Details 詳細情報について

  • CRID
    1574231877186608896
  • NII Article ID
    110003309654
  • NII Book ID
    AN10013254
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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