Author,Title,Journal,ISSN,Publisher,Date,Volume,Number,Page,URL,URL(DOI)
Noriyoshi Itazaki and K. Shimizu and Kozo Kinoshita,Crosstalk fault reduction and simulation for clock-delayed domino circuits,"Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).",,IEEE Comput. Soc,2003-06-26,,,176-181,https://cir.nii.ac.jp/crid/1870020693076027136,https://doi.org/10.1109/ats.2002.1181707