著者名,論文名,雑誌名,ISSN,出版者名,出版日付,巻,号,ページ,URL,URL(DOI)
Tomoya Kitai and Tomohiro Yoneda,Partial order reduction in verification of wheel structured parameterized circuits,Proceedings 2001 Pacific Rim International Symposium on Dependable Computing,,IEEE Comput. Soc,2002-11-14,,,173-182,https://cir.nii.ac.jp/crid/1872272493075591680,https://doi.org/10.1109/prdc.2001.992695