著者名,論文名,雑誌名,ISSN,出版者名,出版日付,巻,号,ページ,URL,URL(DOI) T. Ito and N. Tomabechi,Pipelined design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers,"2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering. TENCOM '02. Proceedings.",,IEEE,2004-03-01,,,412-415,https://cir.nii.ac.jp/crid/1874242817292541568,https://doi.org/10.1109/tencon.2002.1181301