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On-Chip Delay Measurement for Degradation Detection and Its Evaluation under Accelerated Life Test

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type:Journal Article

Periodical delay measurement in field is useful for not only detection of delay-related faults but also prediction of faults due to aging. Logic BIST with variable test clock generation enables on-chip delay measurement in field. This paper addresses a delay measurement scheme based on logic BIST and gives experiment results to observe aging phenomenon of test chips under accelerated life test. The measurement scheme consists of scan-based logic BIST, a variable test clock generator, and digital temperature and voltage sensors. The sensors are used to compensate measured delay values for temperature and voltage variations in field. Evaluation using SPICE simulation shows that the scheme can measure a circuit delay with resolution of 92 ps. The delay measurement scheme is also implemented on fabricated test chips with 180 nm CMOS technology and accelerated test is performed using ATE and burn-in equipment. Experimental results show that a circuit delay increased 552 ps when accelerated the chip for 3000 hours. It is confirmed that the on-chip delay measurement scheme has enough accuracy for detection of aging-induced delay increase.

26th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2020), 13-15 July, 2020, Napoli, Italy(新型コロナ感染拡大に伴い、オンライン開催に変更)

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詳細情報

  • CRID
    1050850623758938496
  • ISSN
    1942-9401
    1942-9398
  • Web Site
    http://hdl.handle.net/10228/00008150
  • 本文言語コード
    en
  • 資料種別
    journal article
  • データソース種別
    • IRDB
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