A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry
Bibliographic Information
- Title
- A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry
- Author
- A.Mochizuki
Journal
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- 2005 Symposium on VLSI Circuits
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2005 Symposium on VLSI Circuits 264-267, 2005
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Details 詳細情報について
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- CRID
- 1010000781808677260
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- Article Type
- journal article
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- Data Source
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- KAKEN