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A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry
Bibliographic Information
- Title
- A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry
- Author
- A.Mochizuki
Journal
-
- 2005 Symposium on VLSI Circuits
-
2005 Symposium on VLSI Circuits 264-267, 2005
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Details 詳細情報について
-
- CRID
- 1010000781808677260
-
- Article Type
- journal article
-
- Data Source
-
- KAKEN
