A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry
書誌事項
- タイトル
- A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry
- 著者
- A.Mochizuki
収録刊行物
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- 2005 Symposium on VLSI Circuits
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2005 Symposium on VLSI Circuits 264-267, 2005