2 フェイズ ・ ハンドシェイクプロトコルに基づく束データ非同期式回路において，PVT ばらつきに起因する遅延値の変動が存在し，その対策として，一般的に十分なマージンをとった遅延素子が用いられるが，その代償として余剰マージンによる遅延値の増大が発生する．本稿では従来の遅延線と比較し，よりマージンの少ない遅延線を生成する手法を提案する．提案手法は 6 段のインバータからなる遅延素子の 2，5 段目の pMOS,nMOS 段数を 2 ～ 4 まで変更したものを最適に組み合わせることによって成る．遅延値のマージン，消費電力の面において，一般的な遅延素子およびバッファを組み合わせた遅延線と比較することにより，提案手法の有効性を示す．

The delay variations due to PVT variations are one of serious issues in bundled-data transfer asynchronous circuits based on the two-phase handshaking protocols. Several delay elements with a sufficient margin are widely used in order to satisfy the matched delay constraint. However, they may cause a significant performance reduction due to a redundant margin. In this paper, we propose a design method to generate the appropriate delayline with less margin compared to the conventional delaylines considering delay variations due to PVT variations. In the proposed method, delay elements which consist of six inverter chains are used in order to adjust their rising delays to their falling delays for the 2phase handshaking protocol. The numbers of pMOS (nMOS) stacks in the second and the fifth inverters in the delay elements are varied from 2 to 4 in order to match their delay variations to those of the corresponding combinational circuit. In terms of the margin of delay values and power consumption, we show the effectiveness of the proposed method by comparing with the conventional delaylines which consist of the general delay elements and buffers.