Cascading ALU Operations for Improving Timing Yield (in japanese)'', IPSJ Transactions on Advanced Computing Systems

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  • Watanabe, Shingo
    Department of Artificial Intelligence, Kyushu Institute of Technology
  • Hashimoto, Masanori
    Department of Information Systems Engineering, Osaka University
  • Sato, Toshinori
    Department of Electronics Engineering and Computer Science, Fukuoka University,Kyushu University,Japan Science and Technology Agency, CREST

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Other Title
  • タイミング歩留まり改善を目的とする演算カスケーディング
  • タイミング ブドマリ カイゼン オ モクテキ ト スル エンザン カスケーディング

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Abstract

As semiconductor technologies are aggressively advanced, the problem of parameter variations is emerging. Parameter variations in transistors affect circuit delay, resulting in serious yield loss. We exploit the statistical characteristics in circuit delay, and investigate a cascading technique of ALU operations for variation reduction. From the statistical timing analysis in circuit level and the performance evaluation in processor level, this paper tries to unveil how efficiently the cascading technique improves timing yield of processors. We find that innovations are required for managing parameter variations in microarchitecture level.

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