Dynamically Programmable Parallel Processor (DPPP) : A Novel Reconfigurable Architecture with Simple Program Interface

HANDLE 4 Citations 15 References Open Access

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Abstract

This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm × 4.5 mm chip using 0.6 µm CMOS process.

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Details 詳細情報について

  • CRID
    1050018218950027392
  • NII Article ID
    110003210431
  • NII Book ID
    AA10826272
  • HANDLE
    11094/51672
  • ISSN
    09168532
  • Text Lang
    en
  • Article Type
    journal article
  • Data Source
    • IRDB
    • CiNii Articles

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