Design Study of Domain Decomposition Operation in Dataflow Architecture FDTD/FIT Dedicated Computer

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  • データフローアーキテクチャFDTD法/FIT専用計算機における領域分割法の実装に関する研究
  • データフローアーキテクチャ FDTDホウ/FIT センヨウ ケイサンキ ニ オケル リョウイキ ブンカツホウ ノ ジッソウ ニ カンスル ケンキュウ

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Abstract

To aim achieve a high-performance computation for microwave simulations with low cost, small size machine and low energy consumption, author has been working in development of the FDTD method dedicated computer with dataflow architecture. It was shown by VHDL logical circuit simulations of the FDTD machine that the designed architecture has much higher performance than that of high-end PC and GPU. However it was also found that microwave simulation for only 25 x 25 grid space in x-y plane can be executed in a single FPGA at most. To treat much larger numerical model size for practical applications, this paper considers implementation of a domain decomposition method operation of the FDTD dedicated computer in single FPGA.

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