An Optimum Design of FFT Multi-Digit Multiplier and Its VLSI Implementation

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  • Optimum Design of FFT Multi Digit Multiplier and Its VLSI Implementation

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We designed a VLSI chip of FFT multiplier based on simple Cooly-Tukey FFT using a floating-pointrepresentation with optimal data length based on an experimental error analysis. The VLSIimplementation using HITACHI CMOS 0.18 μm technology can perform multiplication of 25 to 213digit hexadecimal numbers 19.7 to 34.3 times (25.7 times in average) faster than software FFTmultiplier at an area cost of 9.05mm2 . The hardware FFT multiplier is 35.7 times faster than thesoftware FFT multiplier for multiplication of 221 digit hexadecimal numbers. Advantage ofhardware FFT multiplier over software will increase when more sophisticated FFT architecturesare applied to the multiplier.

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