チューナブル・アーキテクチャ計算機システムにおけるチューニング過程について

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  • A Tuning Process in a Tunable Archtecture Computer System
  • チューナブル アーキテクチャ ケイサンキ システム ニ オケル チューニング

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A tuning process in a tunable archtecture computer is described. We have designed a computer system with tunable archtecture. Main components of this computer are four AM2903 bit-slice chips. The control schema of micro instructions is horizontal-type, and the length of each instruction is 104 bits. Our tunable algorithm utilizes an execution history of machine level instructions, because the execution history can be regarded as a property of the user program. In execution histories of similar programs, same sequences of machine instructions must appear. Each sequence is synthesized into a new machine instruction by means of microprogramming. In order to select new machine instructions, this algorithm uses not only the enlarged amount of necessary control storage but also the improvement of execution efficiency.

A tuning process in a tunable archtecture computer is described. We have designed a computer system with tunable archtecture. Main components of this computer are four AM2903 bit-slice chips. The control schema of micro instructions is horizontal-type, and the length of each instruction is 104 bits. Our tunable algorithm utilizes an execution history of machine level instructions, because the execution history can be regarded as a property of the user program. In execution histories of similar programs, same sequences of machine instructions must appear. Each sequence is synthesized into a new machine instruction by means of microprogramming. In order to select new machine instructions, this algorithm uses not only the enlarged amount of necessary control storage but also the improvement of execution efficiency.

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