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On-chip interconnects are becoming a major power consumer in scaled VLSI design. Consequently bus power reduction has become effective for total power reduction on chip multiprocessors and system-on-a-chip requiring long interconnects as buses. In this paper we advocate the use of bus serialization to reduce bus power consumption. Bus serialization decreases the number of wires and increases the pitch between the wires. The wider pitch decreases the coupling capacitances of the wires and consequently reduces bus power consumption. Evaluation results indicate that our technique can reduce bus power consumption by 30% in the 45nm technology process.
On-chip interconnects are becoming a major power consumer in scaled VLSI design. Consequently, bus power reduction has become effective for total power reduction on chip multiprocessors and system-on-a-chip requiring long interconnects as buses. In this paper, we advocate the use of bus serialization to reduce bus power consumption. Bus serialization decreases the number of wires and increases the pitch between the wires. The wider pitch decreases the coupling capacitances of the wires, and consequently reduces bus power consumption. Evaluation results indicate that our technique can reduce bus power consumption by 30% in the 45nm technology process.
収録刊行物
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- 情報処理学会論文誌コンピューティングシステム（ACS）
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情報処理学会論文誌コンピューティングシステム（ACS） 47 (SIG3(ACS13)), 49-57, 2006-03-15
東京 : 情報処理学会
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詳細情報 詳細情報について
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- CRID
- 1050564287846594816
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- NII論文ID
- 110004708861
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- NII書誌ID
- AA11833852
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- ISSN
- 18827829
- 03875806
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- NDL書誌ID
- 7888820
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- 本文言語コード
- en
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