アナログ回路のパラメータを最適化するにあたって，線形分類器でシミュレーション前に性能指標を予測することで，探索時間を短縮できる手法を提案した．この手法では線形分類器により探索空間内で最適化に寄与しない領域 (非対象領域) を刈り込めることを前提としている．しかし，線形分類器による刈り込みは探索空間を直線的に切り取るため対象領域の形状によっては十分に不要な空間を刈り込めない，もしくは対象領域を刈り取ってしまう可能性がある．本論文では非線形分類器による刈り込みと比較を行ない，線形分類器による刈り込みであっても非線形分類器と同等の性能を達成できることを確認した．

In this paper, we propose a method to reduce searching time in analog circuit optimization by using linear classifiers. In design space of analog circuit optimization, space where all transistors are in saturation region is very small. But, the edge of the target space is not linear. So, it is not clear whether the linear classifiers always trim adequately or not. This paper compares linear classifiers and non-linear classifiers in analog circuit optimization. Simulation results shows that the optimization results using linear classifier is similar to that using non-linear classifiers. We call this space as “target space”. The data where transistor operates in linear or cutoff region does not contribute to the optimization. The role of the linear classifiers is to trim non-target spaces. But, the edge of the target space is not linear. So, it is not clear whether the linear classifiers always trim adequately or not. This paper compares linear classifiers and non-linear classifiers in analog circuit optimization. Simulation results shows that the optimization results using linear classifier is similar to that using non-linear classifiers.