書誌事項
- タイトル別名
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- LSI multi-layer routing method using a flow graph
- フローグラフ ニヨル LSI タソウ ハイセン モンダイ ノ カイホウ
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抄録
Advances in VLSI fabrication technology have made it possible to use more than two routing layers for interconnection. In such a multi-layer routing technology, one of the important objective functions is via-minimization, that is, the number of vias should be kept as small as possible. A topological planar routing (TPR) was proposed to solve this via-minimization problem. TPR is a layer assignment method which assigns each net to one of the layers without crossing other nets in the same layer. Although an optimum TPR is unfortunately known as an NP-complete problem, it can be approximately solved in polynomial time for the channel layout model as a minimum-cost maximum-flow problem using a flow graph. In this paper, we propose an improved TPR for more general layout model like a macrocell layout model, where planarity testing and a flow graph are modified to treat our model. An experimental result shows that our improvements increase an efficiency of usage of multi-layers.
収録刊行物
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- 山口大学工学部研究報告
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山口大学工学部研究報告 45 (1), 83-90, 1994-10
山口大学工学部
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詳細情報 詳細情報について
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- CRID
- 1050845762384335744
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- NII論文ID
- 110000216970
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- NII書誌ID
- AN00244228
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- ISSN
- 03727661
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- NDL書誌ID
- 3904932
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- 本文言語コード
- ja
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- 資料種別
- departmental bulletin paper
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- データソース種別
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- IRDB
- NDL
- CiNii Articles