ECCを用いた耐マルチビットソフトエラー高位合成について

IPSJ

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This paper discusses the Multiple Bit Upset (MBU) problem on Application Specific Integrated Circuit (ASIC). It focuses especially on the storage part (register) of ASIC since the transient error on registers can be quickly propagated to the other part of the system. It proposes a novel high-level synthesis where a set of registers and error correcting code modules against MBU are grouped to maximize the reliability of ASIC with low cost. It also proposes a heuristic-based algorithm to find optimal data covering, and experimental results to show the effectiveness of the proposed method.

This paper discusses the Multiple Bit Upset (MBU) problem on Application Specific Integrated Circuit (ASIC). It focuses especially on the storage part (register) of ASIC since the transient error on registers can be quickly propagated to the other part of the system. It proposes a novel high-level synthesis where a set of registers and error correcting code modules against MBU are grouped to maximize the reliability of ASIC with low cost. It also proposes a heuristic-based algorithm to find optimal data covering, and experimental results to show the effectiveness of the proposed method.

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