Low-Power High-Performance Intelligent Camera Framework ROS-FPGA Node

情報処理学会

説明

In this work, we proposed a ROS-FPGA node for lane detection based on a ROS-compliant FPGA component on PYNQ-Z2 to support the complexity of the Advanced Driver-Assistance System (ADAS). In the preliminary experiment, the investment algorithm of lane detection based on High-Level Synthesis (HLS) was implemented on Programmable Logic (PL), and the traditional lane detection based on OpenCV was implemented on Processing System (PS) to compare the operation time. The PL fabric clock was 125 MHz, and the CPU clock was 650 MHz. The resolution of the input image was fixed to 400x520 pixels. We found that the processing speed of the lane detection algorithm on PL was 24 FPS and about four times faster than the lane detection on PS.

In this work, we proposed a ROS-FPGA node for lane detection based on a ROS-compliant FPGA component on PYNQ-Z2 to support the complexity of the Advanced Driver-Assistance System (ADAS). In the preliminary experiment, the investment algorithm of lane detection based on High-Level Synthesis (HLS) was implemented on Programmable Logic (PL), and the traditional lane detection based on OpenCV was implemented on Processing System (PS) to compare the operation time. The PL fabric clock was 125 MHz, and the CPU clock was 650 MHz. The resolution of the input image was fixed to 400x520 pixels. We found that the processing speed of the lane detection algorithm on PL was 24 FPS and about four times faster than the lane detection on PS.

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