High-Speed Demonstration of Bit-Serial Floating-Point Adders and Multipliers Using Single-Flux-Quantum Circuits
書誌事項
- 公開日
- 2015-06
- 資源種別
- journal article
- 権利情報
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- https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html
- DOI
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- 10.1109/tasc.2014.2382973
- 公開者
- Institute of Electrical and Electronics Engineers (IEEE)
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説明
We have been developing a large-scale reconfigurable data path (LSRDP) based on single-flux-quantum (SFQ) circuit technology for high-performance computing systems. In the SFQ LSRDP, a large number of SFQ floating-point adders (FPAs) and floating-point multipliers (FPMs) are directly connected to each other through routing networks to reduce a memory access rate. In this paper, we show our recent results about the SFQ FPAs and FPMs. Utilization of the National Institute of Advanced Industrial Science and Technology's 10-kA/cm 2 Nb process makes it possible to accelerate the clock frequency to more than 50 GHz. We successfully demonstrated the high-speed operation of single- precision FPAs and FPMs, whose clock frequency is beyond 50 GHz, by on-chip high-speed tests. We estimate the performance and energy efficiency of SFQ FPAs and FPMs based on the designed circuits.
収録刊行物
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- IEEE Transactions on Applied Superconductivity
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IEEE Transactions on Applied Superconductivity 25 (3), 1-6, 2015-06
Institute of Electrical and Electronics Engineers (IEEE)
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詳細情報 詳細情報について
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- CRID
- 1360004235391075840
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- ISSN
- 15582515
- 10518223
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- 資料種別
- journal article
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- データソース種別
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- Crossref
- KAKEN
- OpenAIRE
