Design of Class-E Amplifier With MOSFET Linear Gate-to-Drain and Nonlinear Drain-to-Source Capacitances
書誌事項
- 公開日
- 2011-10
- 資源種別
- journal article
- 権利情報
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- https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html
- DOI
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- 10.1109/tcsi.2011.2123490
- 公開者
- Institute of Electrical and Electronics Engineers (IEEE)
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説明
This paper presents expressions for the waveforms and design equations to satisfy the ZVS/ZDS conditions in the class-E power amplifier, taking into account the MOSFET gate-to-drain linear parasitic capacitance and the drain-to-source nonlinear parasitic capacitance. Expressions are given for power output capability and power conversion efficiency. Design examples are presented along with the PSpice-simulation and experimental waveforms at 2.3 W output power and 4 MHz operating frequency. It is shown from the expressions that the slope of the voltage across the MOSFET gate-to-drain parasitic capacitance during the switch-off state affects the switch-voltage waveform. Therefore, it is necessary to consider the MOSFET gate-to-drain capacitance for achieving the class-E ZVS/ZDS conditions. As a result, the power output capability and the power conversion efficiency are also affected by the MOSFET gate-to-drain capacitance. The waveforms obtained from PSpice simulations and circuit experiments showed the quantitative agreements with the theoretical predictions, which verify the expressions given in this paper.
収録刊行物
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- IEEE Transactions on Circuits and Systems I: Regular Papers
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IEEE Transactions on Circuits and Systems I: Regular Papers 58 (10), 2556-2565, 2011-10
Institute of Electrical and Electronics Engineers (IEEE)
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詳細情報 詳細情報について
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- CRID
- 1360004235397036032
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- ISSN
- 15580806
- 15498328
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- 資料種別
- journal article
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- データソース種別
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- Crossref
- KAKEN
- OpenAIRE