Electrical depth profile of <i>p</i>-type GaAs/Ga(As, N)/GaAs heterostructures determined by capacitance–voltage measurements

DOI PDF 被引用文献13件
  • P. Krispin
    Paul-Drude-Institut für Festkörperelektronik, Hausvogteiplatz 5-7, 10117 Berlin, Germany
  • S. G. Spruytte
    Solid State and Photonics Laboratory, Stanford University, Stanford, California 94305
  • J. S. Harris
    Solid State and Photonics Laboratory, Stanford University, Stanford, California 94305
  • K. H. Ploog
    Paul-Drude-Institut für Festkörperelektronik, Hausvogteiplatz 5-7, 10117 Berlin, Germany

書誌事項

公開日
2000-10-01
DOI
  • 10.1063/1.1290449
公開者
AIP Publishing

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<jats:p>Capacitance–voltage measurements on metal-semiconductor contacts are used to examine depth-resolved electrical characteristics of GaAs/Ga(As, N)/GaAs heterostructures. The experimental depth profiles of the carrier concentration are compared with calculations based on self-consistent solutions of the Poisson equation. As-grown Ga(As, N) layers are p type, and hole concentrations of about 3×1016 cm−3 are observed for undoped Ga(As, N) layers with a GaN mole fraction of 3% and thicknesses below 80 nm. This hole concentration is stable during rapid thermal annealing. For a GaN mole fraction of about 3%, the valence band offset between GaAs and Ga(As, N) is found to be +(11±2) meV. The heterointerfaces are of type I. The dominant carrier depletion in as-grown heterostructures is due to donor-like defect levels, which are accumulated at the GaAs-on-Ga(As, N) interface. The amount of these interfacial defects rises remarkably in thicker Ga(As, N) layers, but can be completely removed by rapid thermal annealing after growth. By release spectroscopy, further hole traps with definite level energies are distinguished at the Ga(As, N)-on-GaAs interface, which are probably due to the specific GaAs growth conditions.</jats:p>

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