Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications
書誌事項
- 公開日
- 2004-06
- 権利情報
-
- https://www.elsevier.com/tdm/userlicense/1.0/
- DOI
-
- 10.1016/j.sse.2003.12.014
- 公開者
- Elsevier BV
この論文をさがす
収録刊行物
-
- Solid-State Electronics
-
Solid-State Electronics 48 (6), 947-959, 2004-06
Elsevier BV