Lowering Latency in a High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using an Interleaved Register File
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- Ryota Kashima
- Department of Electronics, Nagoya University, Nagoya, Japan
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- Ikki Nagaoka
- Department of Electronics, Nagoya University, Nagoya, Japan
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- Tomoki Nakano
- Department of Electronics, Nagoya University, Nagoya, Japan
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- Masamitsu Tanaka
- Department of Electronics, Nagoya University, Nagoya, Japan
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- Taro Yamashita
- Department of Electronics, Nagoya University, Nagoya, Japan
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- Akira Fujimaki
- Department of Electronics, Nagoya University, Nagoya, Japan
書誌事項
- 公開日
- 2023-08
- 資源種別
- journal article
- 権利情報
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- https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html
- https://doi.org/10.15223/policy-029
- https://doi.org/10.15223/policy-037
- DOI
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- 10.1109/tasc.2023.3249131
- 公開者
- Institute of Electrical and Electronics Engineers (IEEE)
この論文をさがす
収録刊行物
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- IEEE Transactions on Applied Superconductivity
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IEEE Transactions on Applied Superconductivity 33 (5), 1-6, 2023-08
Institute of Electrical and Electronics Engineers (IEEE)
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詳細情報 詳細情報について
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- CRID
- 1360021390747772800
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- ISSN
- 15582515
- 23787074
- 10518223
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- 資料種別
- journal article
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- データソース種別
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- Crossref
- KAKEN
- OpenAIRE
