Characterization of speed and stability of BiNMOS gates with a bipolar and PMOSFET merged structure
説明
A base and drain merged bipolar-PMOSFET (BiPMOS) structure was examined. A latch-up phenomenon in this structure associated with a parasitic PNP bipolar was investigated and verified experimentally and analytically. From the standpoint of stability in circuit operation a latch-up-free structure was considered. To evaluate the contribution of this technology to circuit speed performance, the structure was applied to a BiNMOS gate. It was found that the delay time if a merged BiNMOS gate was improved by 10-20% compared with that of the conventional BiNMOS gate. Moreover, at a fan-out of 1, this gate achieved a higher speed than the CMOS gate. >
収録刊行物
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- International Technical Digest on Electron Devices
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International Technical Digest on Electron Devices 231-234, 2002-12-04
IEEE
