Novel High Density, Stacked Capacitor MOS RAM

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書誌事項

公開日
1979-01-01
DOI
  • 10.7567/jjaps.18s1.35
公開者
IOP Publishing

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説明

A novel one transistor type MOS RAM cell is successfully developed and achieves a higher degree of integration than realized to date with conventional RAM's. This cell provides a remarkable area reduction and/or an increase in storage capacitance by stacking the main portion of the storage capacitor on the address transistor. It is called a stacked capacitor RAM (STC RAM) cell. This STC cell has a triple level poly-Si structure which consists of poly-Si word line and Al bit line. The stacked capacitor is composed of the poly-Si–Si3N4–poly-Si structure. A 256 bit STC MOS RAM is fabricated with 3 µm technology and operates successfully. The STC RAM cell area, 52.5 µm2, is remarkably smaller than the cell area of conventional RAM's with double level poly-Si gate structures, 160 µm2. The charge stored time in the new STC MOS RAM normally ranged from 0.1 sec to 1 sec at room temperature.

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