Room-temperature single dopant atom quantum dot transistors in silicon, formed by field-emission scanning probe lithography

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  • Zahid Durrani
    Department of Electrical and Electronic Engineering, Imperial College London 1 , South Kensington, London SW7 2AZ, United Kingdom
  • Mervyn Jones
    Department of Electrical and Electronic Engineering, Imperial College London 1 , South Kensington, London SW7 2AZ, United Kingdom
  • Faris Abualnaja
    Department of Electrical and Electronic Engineering, Imperial College London 1 , South Kensington, London SW7 2AZ, United Kingdom
  • Chen Wang
    Department of Electrical and Electronic Engineering, Imperial College London 1 , South Kensington, London SW7 2AZ, United Kingdom
  • Marcus Kaestner
    Institute of Micro- and Nanoelectronics, Department of Micro- and Nanoelectronic Systems (MNES), Ilmenau University of Technology 2 , Gustav-Kirchhoff-Str.1, 98693 Ilmenau, Germany
  • Steve Lenk
    Institute of Micro- and Nanoelectronics, Department of Micro- and Nanoelectronic Systems (MNES), Ilmenau University of Technology 2 , Gustav-Kirchhoff-Str.1, 98693 Ilmenau, Germany
  • Claudia Lenk
    Institute of Micro- and Nanoelectronics, Department of Micro- and Nanoelectronic Systems (MNES), Ilmenau University of Technology 2 , Gustav-Kirchhoff-Str.1, 98693 Ilmenau, Germany
  • Ivo W. Rangelow
    Institute of Micro- and Nanoelectronics, Department of Micro- and Nanoelectronic Systems (MNES), Ilmenau University of Technology 2 , Gustav-Kirchhoff-Str.1, 98693 Ilmenau, Germany
  • Aleksey Andreev
    Hitachi Cambridge Laboratory 3 , J. J. Thomson Avenue, CB3 0HE Cambridge, United Kingdom

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<jats:p>Electrical operation of room-temperature (RT) single dopant atom quantum dot (QD) transistors, based on phosphorous atoms isolated within nanoscale SiO2 tunnel barriers, is presented. In contrast to single dopant transistors in silicon, where the QD potential well is shallow and device operation limited to cryogenic temperature, here, a deep (∼2 eV) potential well allows electron confinement at RT. Our transistors use ∼10 nm size scale Si/SiO2/Si point-contact tunnel junctions, defined by scanning probe lithography and geometric oxidation. “Coulomb diamond” charge stability plots are measured at 290 K, with QD addition energy ∼0.3 eV. Theoretical simulation gives a QD size of similar order to the phosphorous atom separation ∼2 nm. Extraction of energy states predicts an anharmonic QD potential, fitted using a Morse oscillator-like potential. The results extend single-atom transistor operation to RT, enable tunneling spectroscopy of impurity atoms in insulators, and allow the energy landscape for P atoms in SiO2 to be determined.</jats:p>

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