抄録
<jats:p>Three-dimensional (3D) integration and bumpless TSV (Through-Silicon-Via) technologies beyond post-scaling have been described. Since the extreme scaling is limited by physical and economic sense, 3D will be used concurrently with tow-dimensional legacy process. Because vertical wiring in WOW can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used. The low aspect ratio of TSVs allows a higher process margin and throughput in etching and metal filling. Multiple TSVs enable die-to-die connections independently, which improves the total yield in wafer-scale stacking. Stacking at the wafer level drastically increases the processing throughput, and bumpless multi-TSVs provide a yield equivalent to or greater than 2D scaling beyond 22-nm nodes.</jats:p>
収録刊行物
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- ECS Transactions
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ECS Transactions 34 (1), 1011-1016, 2011-03-21
The Electrochemical Society