Low Temperature Poly-Si TFTs Using Solid Phase Crystallization of Very Thin Films and an Electron Cyclotron Resonance Chemical Vapor Deposition Gate Insulator
書誌事項
- 公開日
- 1991-12-01
- 権利情報
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- https://iopscience.iop.org/page/copyright
- https://iopscience.iop.org/info/page/text-and-data-mining
- DOI
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- 10.1143/jjap.30.3724
- 公開者
- IOP Publishing
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説明
<jats:p> Low temperature (<jats:italic>T</jats:italic>≦600°C) polycrystalline silicon thin film transistors (poly-Si TFTs) have been fabricated by solid phase crystallization (SPC) of amorphous silicon (a-Si) films deposited by low pressure chemical vapor deposition (LPCVD). These TFTs are distinguished by the very thin nature of the channel Si layer (25 nm) and the use of an SiO<jats:sub>2</jats:sub> gate insulator deposited by electron cyclotron resonance chemical vapor deposition (ECR-CVD). The present process eliminates the need for hydrogenation and produces mobilities greater than 20 cm<jats:sup>2</jats:sup>/V·s and on/off current ratios greater than 10<jats:sup>7</jats:sup>. </jats:p>
収録刊行物
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- Japanese Journal of Applied Physics
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Japanese Journal of Applied Physics 30 (12S), 3724-, 1991-12-01
IOP Publishing
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詳細情報 詳細情報について
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- CRID
- 1360847871771003136
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- NII論文ID
- 210000030932
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- ISSN
- 13474065
- 00214922
- https://id.crossref.org/issn/00214922
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- データソース種別
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- Crossref
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